From mboxrd@z Thu Jan 1 00:00:00 1970 From: Manu Gautam Subject: Re: [PATCH v3 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SDM845 Date: Wed, 18 Apr 2018 22:08:41 +0530 Message-ID: <23b9ca5a-b708-f142-9906-3f3eadd8c26a@codeaurora.org> References: <1522761761-15262-1-git-send-email-anischal@codeaurora.org> <1522761761-15262-4-git-send-email-anischal@codeaurora.org> <152393708031.51482.15076025836699678476@swboyd.mtv.corp.google.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Amit Nischal , Stephen Boyd Cc: Michael Turquette , Stephen Boyd , Andy Gross , David Brown , Rajendra Nayak , Odelu Kukatla , Taniya Das , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Doug Anderson List-Id: linux-arm-msm@vger.kernel.org Hi Amit, On 4/18/2018 6:33 PM, Amit Nischal wrote: >>> +       /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ >>> +       regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); >>> +       regmap_update_bits(regmap, 0x71028, 0x3, 0x3); >> >> I think we'll have to throw in the pipe clk branch stuff in here too? >> And then drop the pipe clks from the driver? > > All the USB pipe clocks would be taken care. The PCIE pipe branch > clocks would have to be explicitly disabled so as to retain the > memory logic. Otherwise, it would lead to memory corruption in case > the external source is directly disabled without disabling the branch clock. PHY driver is same for both USB and PCIE and both PHYs use pipe_clk. If there is indeed some limitation and pipe_clk cant be left enabled always then I will suggest to not change pipe_clk handling for USB as well. -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project