From: Krzysztof Kozlowski <krzk@kernel.org>
To: Jie Gan <quic_jiegan@quicinc.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Tingwei Zhang <quic_tingweiz@quicinc.com>,
Jinlong Mao <quic_jinlmao@quicinc.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH v1 4/4] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device
Date: Mon, 10 Mar 2025 10:08:18 +0100 [thread overview]
Message-ID: <24d5b56f-5078-4128-be66-436b1755d4b7@kernel.org> (raw)
In-Reply-To: <20250310090407.2069489-5-quic_jiegan@quicinc.com>
On 10/03/2025 10:04, Jie Gan wrote:
> Add interrupts to enable byte-cntr function for TMC ETR devices.
>
> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
> ---
> Dependency:
> prerequisite-message-id: 20250303032931.2500935-11-quic_jiegan@quicinc.com
Which too generated such changelog? Why this cannot be lore link?
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-03-10 9:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 9:04 [PATCH v1 0/4] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-03-10 9:04 ` [PATCH v1 1/4] coresight: tmc: Introduce new APIs to get the RWP offset of ETR buffer Jie Gan
2025-03-10 9:07 ` Krzysztof Kozlowski
2025-03-10 9:14 ` Jie Gan
2025-03-11 16:49 ` Mike Leach
2025-03-12 1:20 ` Jie Gan
2025-03-12 12:54 ` Mike Leach
2025-03-13 1:32 ` Jie Gan
2025-03-13 9:00 ` Jie Gan
2025-03-10 9:04 ` [PATCH v1 2/4] dt-bindings: arm: Add an interrupt property for Coresight CTCU Jie Gan
2025-03-10 9:04 ` [PATCH v1 3/4] coresight: ctcu: Enable byte-cntr for TMC ETR devices Jie Gan
2025-03-13 16:24 ` Suzuki K Poulose
2025-03-14 1:59 ` Jie Gan
2025-03-14 17:33 ` Suzuki K Poulose
2025-03-26 1:35 ` Jie Gan
2025-03-10 9:04 ` [PATCH v1 4/4] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Jie Gan
2025-03-10 9:08 ` Krzysztof Kozlowski [this message]
2025-03-10 9:12 ` Jie Gan
2025-03-12 13:22 ` [PATCH v1 0/4] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-03-13 6:15 ` Jie Gan
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