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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIzMDEzMSBTYWx0ZWRfX8yAklj6AaQoy abGNnnX080NC+Grr11B3t944rIDGHmPLbBrxpH89SQHB6KV2XTU+J6OpPC135hc1gJScJIr8jGq EMa9xUHE2pMSMoycoEmcQtPvwllT/xH2mFzjbDNbC64D1bpA+hGHvJB7qjuCjOZ9Hqho4fVbrAS t7BR8tZvwdbV1f9Qh7mH3M7bAgDNgIz9fSEaO4rvxk4iFE8dZdVCIX+/G02oTioy08vFGYzFkd8 /oPoi9yPCAsFJ/bVtL7os04Z3E6+LqBc+/Yx4qvR0/PTJiJhEEl8vGnkOiynBYbBFDfn0DSjb8a ItRSi1hTVHU30QYst5NpQgZXASUBcjW+M0Ia6dMjcFhI0181FhO66Kf2CuYqayAcNic7lNIEOA5 WQwxzZu38a6A0n89o/tlT82hixHScA== X-Proofpoint-GUID: Vo9y7CoUXV9WHiMXqxfB2A8duLHEyYHR X-Authority-Analysis: v=2.4 cv=bL8b4f+Z c=1 sm=1 tr=0 ts=68faa982 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=OORdEvYNKPdDRPFHMUl15A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=bgAURMIcSi5BoiUHQI0A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: Vo9y7CoUXV9WHiMXqxfB2A8duLHEyYHR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-23_03,2025-10-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510230131 On 10/22/2025 8:57 PM, Konrad Dybcio wrote: > On 10/17/25 7:08 PM, Akhil P Oommen wrote: >> From: Jie Zhang >> >> Add gpu and rgmu nodes for qcs615 chipset. >> >> Signed-off-by: Jie Zhang >> Signed-off-by: Akhil P Oommen >> --- > > [...] > >> + gpu_zap_shader: zap-shader { >> + memory-region = <&pil_gpu_mem>; >> + }; >> + >> + gpu_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-845000000 { >> + opp-hz = /bits/ 64 <845000000>; >> + required-opps = <&rpmhpd_opp_turbo>; >> + opp-peak-kBps = <7050000>; > > Are there speed bins? None I am aware of as of now. > > [...] > >> + rgmu: rgmu@506a000 { >> + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; >> + reg = <0x0 0x0506a000 0x0 0x34000>; >> + reg-names = "gmu"; >> + >> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_CXO_CLK>, >> + <&gcc GCC_DDRSS_GPU_AXI_CLK>, >> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; >> + clock-names = "gmu", >> + "cxo", >> + "axi", >> + "memnoc", >> + "smmu_vote"; >> + >> + power-domains = <&gpucc CX_GDSC>, >> + <&gpucc GX_GDSC>, >> + <&rpmhpd RPMHPD_CX>; >> + power-domain-names = "cx", "gx", "vdd_cx"; > > I think the gpucc node should reference _CX directly instead, > then genpd/opp should trickle the requirements up the chain Do you mean the CX rail scaling here should be handled by gpucc clk driver? > >> + >> + interrupts = , >> + ; >> + interrupt-names = "oob", "gmu"; > > 1 a line, please Ack. Thanks -Akhil > > lgtm otherwise > > Konrad