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Tue, 18 Feb 2025 11:27:44 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51IBRPD8031473 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 18 Feb 2025 11:27:25 GMT Received: from [10.152.195.140] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 18 Feb 2025 03:27:15 -0800 Message-ID: <25e5840d-a9c3-45fa-ae06-e18c387f1efc@quicinc.com> Date: Tue, 18 Feb 2025 16:57:12 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 5/6] arm64: dts: qcom: ipq9574: Add nsscc node To: Konrad Dybcio , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , References: <20250207073926.2735129-1-quic_mmanikan@quicinc.com> <20250207073926.2735129-6-quic_mmanikan@quicinc.com> Content-Language: en-US From: Manikanta Mylavarapu In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8uUAcfAcj6CylrdPtUO1K7NHTHtu96ta X-Proofpoint-ORIG-GUID: 8uUAcfAcj6CylrdPtUO1K7NHTHtu96ta X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-18_04,2025-02-18_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 mlxscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502180090 On 2/10/2025 11:47 PM, Konrad Dybcio wrote: > On 7.02.2025 8:39 AM, Manikanta Mylavarapu wrote: >> From: Devi Priya >> >> Add a node for the nss clock controller found on ipq9574 based devices. >> >> Signed-off-by: Devi Priya >> Signed-off-by: Manikanta Mylavarapu >> --- >> Changes in V9: >> - Rebased on linux-next tip. >> >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 942290028972..29008b156a7e 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -1193,6 +1193,25 @@ pcie0: pci@28000000 { >> status = "disabled"; >> }; >> >> + nsscc: clock-controller@39b00000 { >> + compatible = "qcom,ipq9574-nsscc"; >> + reg = <0x39b00000 0x80000>; >> + clocks = <&xo_board_clk>, >> + <&cmn_pll NSS_1200MHZ_CLK>, >> + <&cmn_pll PPE_353MHZ_CLK>, >> + <&gcc GPLL0_OUT_AUX>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <&gcc GCC_NSSCC_CLK>; > > This last clock doesn't seem to be used in the driver - is that by design? Hi Konrad, Initially, was under the impression that the GCC_NSSCC_CLK will be enabled by the Ethernet driver. However, that is incorrect and this clock is needed for accessing the NSSCC block itself. Hence restoring this. I will enable this clock by using the PM APIs (pm_clk_add()) in next version. Thanks & Regards, Manikanta.