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[83.9.29.233]) by smtp.gmail.com with ESMTPSA id l5-20020a19c205000000b004f871c71827sm212702lfc.139.2023.06.28.04.03.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Jun 2023 04:03:58 -0700 (PDT) Message-ID: <26be53d7-bcbd-618a-0d8a-f1c826dfd426@linaro.org> Date: Wed, 28 Jun 2023 13:03:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH V2 2/5] clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling Content-Language: en-US To: Imran Shaik , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Taniya Das , Melody Olvera , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona , Satya Priya Kakitapalli , Ajit Pandey References: <20230628092837.3090801-1-quic_imrashai@quicinc.com> <20230628092837.3090801-3-quic_imrashai@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230628092837.3090801-3-quic_imrashai@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 28.06.2023 11:28, Imran Shaik wrote: > Fix the gcc_pcie_0_pipe_clk_src clock handling for QDU1000 and > QRU1000 SoCs. > > Fixes: 1c9efb0bc040 ("clk: qcom: Add QDU1000 and QRU1000 GCC support") > Co-developed-by: Taniya Das > Signed-off-by: Taniya Das > Signed-off-by: Imran Shaik > ---You could have explained that clk_regmap_phy_mux_ops doesn't implement any parent-related ops and switches parents implicitly in .enable/disable Reviewed-by: Konrad Dybcio Konrad > Changes since v1: > - Newly added > > drivers/clk/qcom/gcc-qdu1000.c | 23 ++++++----------------- > 1 file changed, 6 insertions(+), 17 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c > index 5051769ad90c..c00d26a3e6df 100644 > --- a/drivers/clk/qcom/gcc-qdu1000.c > +++ b/drivers/clk/qcom/gcc-qdu1000.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #include > @@ -370,16 +370,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { > { .index = DT_TCXO_IDX }, > }; > > -static const struct parent_map gcc_parent_map_7[] = { > - { P_PCIE_0_PIPE_CLK, 0 }, > - { P_BI_TCXO, 2 }, > -}; > - > -static const struct clk_parent_data gcc_parent_data_7[] = { > - { .index = DT_PCIE_0_PIPE_CLK_IDX }, > - { .index = DT_TCXO_IDX }, > -}; > - > static const struct parent_map gcc_parent_map_8[] = { > { P_BI_TCXO, 0 }, > { P_GCC_GPLL0_OUT_MAIN, 1 }, > @@ -439,16 +429,15 @@ static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = { > }, > }; > > -static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { > +static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { > .reg = 0x9d064, > - .shift = 0, > - .width = 2, > - .parent_map = gcc_parent_map_7, > .clkr = { > .hw.init = &(const struct clk_init_data) { > .name = "gcc_pcie_0_pipe_clk_src", > - .parent_data = gcc_parent_data_7, > - .num_parents = ARRAY_SIZE(gcc_parent_data_7), > + .parent_data = &(const struct clk_parent_data){ > + .index = DT_PCIE_0_PIPE_CLK_IDX, > + }, > + .num_parents = 1, > .ops = &clk_regmap_phy_mux_ops, > }, > },