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Wed, 01 Oct 2025 15:00:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHifSlan3h5RBjjCLPaJeaE4EOWmKdwWuMjDg/ZbUeJT6bjRGbcINV4nFTXqWDsiHfMn8qoQA== X-Received: by 2002:a05:6a00:98c:b0:781:b23:6b7e with SMTP id d2e1a72fcca58-78af41efa31mr5716824b3a.15.1759356014792; Wed, 01 Oct 2025 15:00:14 -0700 (PDT) Received: from [192.168.1.9] ([117.244.71.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-78b020938b1sm636738b3a.83.2025.10.01.15.00.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Oct 2025 15:00:14 -0700 (PDT) Message-ID: <26e29a80-df70-4ffb-9cc0-8b1ab74873ce@oss.qualcomm.com> Date: Thu, 2 Oct 2025 03:30:04 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Betterbird (Windows) Subject: Re: [PATCH 13/17] drm/msm/adreno: Support AQE engine To: rob.clark@oss.qualcomm.com Cc: Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20250930-kaana-gpu-support-v1-0-73530b0700ed@oss.qualcomm.com> <20250930-kaana-gpu-support-v1-13-73530b0700ed@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAyOSBTYWx0ZWRfX+QXpd+DCh7pu 5orXoNpZvuh2JcrO7PXnVtBNV7HTUkdMw+8l4psP1gcYVPje952LUFmmGOOFuCo7G+X5FsQGe+I WADCF91takunuWphw/W+3aq53qGv2eVC8HQ8HVQraucrRLj9bVc5hm0Y4kppcfVJoRUBcP/wian AUZzBR6ARq3qbxbN/jiZYZAwG9p7Y/sjTsd1knXEe5Pe9bPpTAkg1WKn/eyT/t6yotLiTU3mxAO o5+hS4II0W3Pw2ttip2Ob6z+UpA7p7sf0mhfKX7mRB1/cyqGj4axseE57xb1gH2qZs64Z6jGHjM OBzC9zoJGtNt9cKDPeEQJ+oMft4lpfChK0Ra3TkJasxlIOfRq6NqJHs8+oRI+fvMl/2U+4W4KV7 UKf2fx+Tkls9ZDgD8TNPU8GuMquniA== X-Proofpoint-GUID: KvFblcwXBabU-quAdeepDY33iaoKp-oa X-Authority-Analysis: v=2.4 cv=OMkqHCaB c=1 sm=1 tr=0 ts=68dda473 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=2kejHg7nZSoTgEpwAwsXNQ==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=neJfBgYAGg7YAZYFY1IA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: KvFblcwXBabU-quAdeepDY33iaoKp-oa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-01_06,2025-09-29_04,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270029 On 9/30/2025 1:57 PM, Rob Clark wrote: > On Mon, Sep 29, 2025 at 10:51 PM Akhil P Oommen > wrote: >> >> AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides >> in Raytracing related workloads. Add support for loading the AQE firmware >> and initialize the necessary registers. >> >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 24 ++++++++++++++++++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 ++ >> drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 3 +++ >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + >> 4 files changed, 30 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 4aeeaceb1fb30a9d68ac636c14249e3853ef73ac..07ac5be9d0bccf4d2345eb76b08851a94187e861 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -1093,6 +1093,30 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) >> } >> } >> >> + if (!a6xx_gpu->aqe_bo && adreno_gpu->fw[ADRENO_FW_AQE]) { >> + a6xx_gpu->aqe_bo = adreno_fw_create_bo(gpu, >> + adreno_gpu->fw[ADRENO_FW_AQE], &a6xx_gpu->aqe_iova); >> + >> + if (IS_ERR(a6xx_gpu->aqe_bo)) { >> + int ret = PTR_ERR(a6xx_gpu->aqe_bo); >> + >> + a6xx_gpu->aqe_bo = NULL; >> + DRM_DEV_ERROR(&gpu->pdev->dev, >> + "Could not allocate AQE ucode: %d\n", ret); >> + >> + return ret; >> + } >> + >> + msm_gem_object_set_name(a6xx_gpu->aqe_bo, "aqefw"); >> + if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->aqe_bo)) { > > a6xx_ucode_check_version() doesn't do anything for aqe fw (but also > a6xx_ucode_check_version() should probably bail early for a8xx at this > point?) > > OTOH if over time we keep growing the version checks, we might need to > re-think how a6xx_ucode_check_version() works. But that is not a now > problem. Copy-paste miss. We can remove a6xx_ucode_check_version() until there are some security or any other major fixes in AQE firmware. -Akhil. > > BR, > -R > >> + msm_gem_unpin_iova(a6xx_gpu->aqe_bo, gpu->vm); >> + drm_gem_object_put(a6xx_gpu->aqe_bo); >> + >> + a6xx_gpu->aqe_bo = NULL; >> + return -EPERM; >> + } >> + } >> + >> /* >> * Expanded APRIV and targets that support WHERE_AM_I both need a >> * privileged buffer to store the RPTR shadow >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >> index 18300b12bf2a8bcd5601797df0fcc7afa8943863..a6ef8381abe5dd3eb202a645bb87a3bc352df047 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h >> @@ -58,6 +58,8 @@ struct a6xx_gpu { >> >> struct drm_gem_object *sqe_bo; >> uint64_t sqe_iova; >> + struct drm_gem_object *aqe_bo; >> + uint64_t aqe_iova; >> >> struct msm_ringbuffer *cur_ring; >> struct msm_ringbuffer *next_ring; >> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> index 6a64b1f96d730a46301545c52a83d62dddc6c2ff..9a09ce37687aba2f720637ec3845a25d72d2fff7 100644 >> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c >> @@ -599,6 +599,9 @@ static int hw_init(struct msm_gpu *gpu) >> goto out; >> >> gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); >> + if (a6xx_gpu->aqe_iova) >> + gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova); >> + >> /* Set the ringbuffer address */ >> gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); >> gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> index 6a2157f31122ba0c2f2a7005c98e3e4f1ada6acc..3de3a2cda7a1b9e6d4c32075afaadc6604e74b15 100644 >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >> @@ -27,6 +27,7 @@ enum { >> ADRENO_FW_PFP = 1, >> ADRENO_FW_GMU = 1, /* a6xx */ >> ADRENO_FW_GPMU = 2, >> + ADRENO_FW_AQE = 3, >> ADRENO_FW_MAX, >> }; >> >> >> -- >> 2.51.0 >>