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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c9564865sm81412866b.108.2025.01.09.07.20.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Jan 2025 07:20:59 -0800 (PST) Message-ID: <27ae4821-b185-41ba-a0ed-6e4f754a4484@oss.qualcomm.com> Date: Thu, 9 Jan 2025 16:20:58 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] arm64: dts: qcom: sm8650: rework CPU & GPU thermal zones To: neil.armstrong@linaro.org, Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , robclark@freedesktop.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250103-topic-sm8650-thermal-cpu-idle-v1-0-faa1f011ecd9@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 63WJ89M6GnsRGrY61LqoSU9CJ1AfNpOA X-Proofpoint-GUID: 63WJ89M6GnsRGrY61LqoSU9CJ1AfNpOA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 impostorscore=0 adultscore=0 mlxscore=0 mlxlogscore=815 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501090122 On 3.01.2025 3:49 PM, Neil Armstrong wrote: > On 03/01/2025 15:43, Konrad Dybcio wrote: >> On 3.01.2025 3:38 PM, Neil Armstrong wrote: >>> On the SM8650 platform, the dynamic clock and voltage scaling (DCVS) for >>> the CPUs and GPU is handled by hardware & firmware using factory and >>> form-factor determined parameters in order to maximize frequency while >>> keeping the temperature way below the junction temperature where the SoC >>> would experience a thermal shutdown if not permanent damages. >>> >>> On the other side, the High Level Ooperating System (HLOS), like Linux, >>> is able to adjust the CPU and GPU frequency using the internal SoC >>> temperature sensors (here tsens) and it's UP/LOW interrupts, but it >>> effectly does the same work twice in an less effective manner. >>> >>> Let's take the Hardware & Firmware action in account and design the >>> thermal zones trip points and cooling devices mapping to use the HLOS >>> as a safety warant in case the platform experiences a temperature surge >>> to helpfully avoid a thermal shutdown and handle the scenario gracefully. >>> >>> On the CPU side, the LMh hardware does the DCVS control loop, so >>> let's set higher trip points temperatures closer to the junction >>> and thermal shutdown temperatures and add some idle injection cooling >>> device with 100% duty cycle for each CPU that would act as emergency >>> action to avoid the thermal shutdown. >>> >>> On the GPU side, the GPU Management Unit (GMU) acts as the DCVS >>> control loop, but since we can't perform idle injection, let's >>> also set higher trip points temperatures closer to the junction >>> and thermal shutdown temperatures to reduce the GPU frequency only >>> as an emergency action before the thermal shutdown. We could probably work out some mechanism for drm to say "gpu is too hot / too busy" and stall the userspace's requests.. If that doesn't exist already (+RobC) >>> >>> Those 2 changes optimizes the thermal management design by avoiding >>> concurrent thermal management, calculations & avoidable interrupts >>> by moving the HLOS management to a last resort emergency if the >>> Hardware & Firmwares fails to avoid a thermal shutdown. >>> >>> Signed-off-by: Neil Armstrong >>> --- >> >> Got any numbers to back this? > > To back which part ? Yes I've been running loads with difference > scenarios and effectively the hardware work is much better with > a more linear correction and slighly better performances because > it sets slighly higger OPPs while maintaining the core closer to > the target temperature range. Which is kind of expected. > > I don't have easy numbers to share, sorry... Ok, what you said above sounds good already. Konrad