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Tue, 28 Apr 2026 20:05:04 -0700 (PDT) X-Received: by 2002:a17:902:eec2:b0:2b4:5f67:5914 with SMTP id d9443c01a7336-2b987442b4fmr14370415ad.33.1777431903925; Tue, 28 Apr 2026 20:05:03 -0700 (PDT) Received: from [10.92.193.222] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b988940d08sm5813365ad.43.2026.04.28.20.04.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Apr 2026 20:05:03 -0700 (PDT) Message-ID: <28c30ddb-f46a-458d-9680-eac1ce8c5b68@oss.qualcomm.com> Date: Wed, 29 Apr 2026 08:34:58 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields To: =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, LKML , mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com, Shawn Lin References: <20260428-t_power_on_fux-v5-0-f1ef926a91ff@oss.qualcomm.com> <20260428-t_power_on_fux-v5-1-f1ef926a91ff@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: rU95zUEKM_Wwjc8Rnldg0uBhkkWSQegu X-Proofpoint-ORIG-GUID: rU95zUEKM_Wwjc8Rnldg0uBhkkWSQegu X-Authority-Analysis: v=2.4 cv=BfDoFLt2 c=1 sm=1 tr=0 ts=69f17561 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=s8YR1HE3AAAA:8 a=EUspDBNiAAAA:8 a=QyXUC8HyAAAA:8 a=Zlw8WEmqWycuYniGgb4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=jGH_LyMDp9YhSvY-UuyI:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDAyNiBTYWx0ZWRfXwugvxCTi6VcG a9bQ1Hqj/UnaG+/Gcfr/pZ0Ua+5XMpKx9FEKNlIMera6FYtQQMxloAUNR2w3aA5Y7ebgXtBSexO L4Hgilsmpf7l79iq6K2zmmnljvymK8qNhB62dcQdNoaamuvmKNpI4aZMBvB43s+WWnxGD1QmZzf iuIW8+R10EtMzBIuNW9p++pzQht6/db0EIgUOZzFVi5gQ8I6REZAtjXz/z762susgG+yJ77Z7zv 8XhdlClzFYmxvu91OXhT3Fu/7ix/onIQtDfJ2EvweKs2Q+YMnGHf9xgpkF1NvDLJq3SScMkh8Hi +y2c6n5q6uj03Da9LI9T4IIdriX9+tun3cfW/87AxvmdAr2wTJFv6AyyQ5BHQd6rjApfqVWVRYA PMsZ6wCvqMOkNMBYtiJSj/yo2wZig0cXjw2hUi1Yb22SKs4HwGqps6PAM+mbfTEwgfgNYvz2DBu bCs8KCS+uWAY/7/af5Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290026 On 4/28/2026 2:57 PM, Ilpo Järvinen wrote: > On Tue, 28 Apr 2026, Krishna Chaitanya Chundru wrote: > >> Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON >> parameter into the T_POWER_ON Scale and T_POWER_ON Value fields. >> >> This helper can be used by the controller drivers to change the >> default/wrong value of T_POWER_ON in L1ss capability register to >> avoid incorrect calculation of LTR_L1.2_THRESHOLD value. >> >> The helper converts a T_POWER_ON time specified in microseconds into >> the appropriate scale/value encoding defined by the PCIe spec r7.0, >> sec 7.8.3.2. Values that exceed the maximum encodable range are clamped >> to the largest representable encoding. >> >> Tested-by: Shawn Lin >> Reviewed-by: Shawn Lin >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/pci.h | 6 ++++++ >> drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 46 insertions(+) >> >> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h >> index 4a14f88e543a..c379befe1ebe 100644 >> --- a/drivers/pci/pci.h >> +++ b/drivers/pci/pci.h >> @@ -1110,6 +1110,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); >> void pcie_aspm_powersave_config_link(struct pci_dev *pdev); >> void pci_configure_ltr(struct pci_dev *pdev); >> void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value); >> #else >> static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } >> static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } >> @@ -1118,6 +1119,11 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) >> static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } >> static inline void pci_configure_ltr(struct pci_dev *pdev) { } >> static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } >> +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) >> +{ >> + *scale = 0; >> + *value = 0; >> +} >> #endif >> >> #ifdef CONFIG_PCIE_ECRC >> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c >> index 925373b98dff..457d469b8d49 100644 >> --- a/drivers/pci/pcie/aspm.c >> +++ b/drivers/pci/pcie/aspm.c >> @@ -525,6 +525,46 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val) >> return 0; >> } >> >> +/** >> + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields >> + * @t_power_on_us: T_POWER_ON time in microseconds >> + * @scale: Encoded T_POWER_ON Scale (0..2) >> + * @value: Encoded T_POWER_ON Value >> + * >> + * T_POWER_ON is encoded as: >> + * T_POWER_ON(us) = scale_unit(us) * value >> + * >> + * where scale_unit is selected by @scale: >> + * 0: 2us >> + * 1: 10us >> + * 2: 100us >> + * >> + * If @t_power_on_us exceeds the maximum representable value, the result >> + * is clamped to the largest encodable T_POWER_ON. >> + * >> + * See PCIe r7.0, sec 7.8.3.2. >> + */ >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) > Hi, > > I don't know how the type for t_power_on_us was picked but if it was > arbitrary decision, I suggest you just go with 32-bit input. The maximum value of the T power ON is 3100us, so we are using u16 here. - Krishna Chaitanya. > That would also remove the u32 -> u16 truncate done in the other patches > of your series which would potentially corrupt the number (I assume > numbers that big would be invalid but they could alias to small u16 > numbers). > > Reviewed-by: Ilpo Järvinen > >> +{ >> + u8 maxv = FIELD_MAX(PCI_L1SS_CAP_P_PWR_ON_VALUE); >> + >> + /* T_POWER_ON_Value ("value") is a 5-bit field with max value of 31. */ >> + if (t_power_on_us <= 2 * maxv) { >> + *scale = 0; /* Value times 2us */ >> + *value = DIV_ROUND_UP(t_power_on_us, 2); >> + } else if (t_power_on_us <= 10 * maxv) { >> + *scale = 1; /* Value times 10us */ >> + *value = DIV_ROUND_UP(t_power_on_us, 10); >> + } else if (t_power_on_us <= 100 * maxv) { >> + *scale = 2; /* value times 100us */ >> + *value = DIV_ROUND_UP(t_power_on_us, 100); >> + } else { >> + *scale = 2; >> + *value = maxv; >> + } >> +} >> +EXPORT_SYMBOL(pcie_encode_t_power_on); >> + >> /* >> * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1 >> * register. Ports enter L1.2 when the most recent LTR value is greater >> >>