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To: Andrew Lunn CC: Vinod Koul , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Jose Abreu , Maxime Coquelin , , , , , , References: <20241225-support_10m100m-v1-0-4b52ef48b488@quicinc.com> <6dcfdb0b-c1ec-49f7-927e-531b20264d68@lunn.ch> Content-Language: en-US From: Yijie Yang In-Reply-To: <6dcfdb0b-c1ec-49f7-927e-531b20264d68@lunn.ch> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: aT-qbS5--U28yytijSEuIIvt2WmkGe8Z X-Proofpoint-GUID: aT-qbS5--U28yytijSEuIIvt2WmkGe8Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 adultscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=527 malwarescore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412260025 On 2024-12-26 01:49, Andrew Lunn wrote: > On Wed, Dec 25, 2024 at 06:04:44PM +0800, Yijie Yang wrote: >> The Ethernet MAC requires precise sampling times at Rx, but signals on the >> Rx side after transmission on the board may vary due to different hardware >> layouts. The RGMII_CONFIG2_RX_PROG_SWAP can be used to switch the sampling >> occasion between the rising edge and falling edge of the clock to meet the >> sampling requirements. > > The RGMII specification says that RD[3:0] pins are sampled on the > rising edge for bits 3:0 and falling edge for bits 7:4. > > Given this is part of the standard, why would you want to do anything > else? > > Is this maybe another symptom of having the RGMII delays messed up? > > Anyway, i don't see a need for this property, unless you are working > with a PHY which breaks the RGMII standard, and has its clock > reversed? Please correct me if there are any errors. As described in the Intel and TI design guidelines, Dual Data Rate (DDR), which samples at both edges of the clock, is primarily used for 1Gbps speeds. For 100Mbps and 10Mbps speeds, Single Data Rate (SDR), which samples at the rising edge of the clock, is typically adopted. This patch set introduces such a flag mainly for 100M/10M speeds, as described in the cover letter. > > Andrew -- Best Regards, Yijie