Re: [PATCH 2/3] arm64: dts: qcom: Introduce Eliza Soc base dtsi

[Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>]

On 24/02/2026 14:06, Konrad Dybcio wrote:
> On 2/24/26 1:13 PM, Abel Vesa wrote:
>> Introduce the initial support for the Qualcomm Eliza SoC.
>> It is a high-tier SoC designed for mobile platforms.
>>
>> The initial submission enables support for:
>> - CPU nodes with cpufreq and cpuidle support
>> - Global Clock Controller (GCC)
>> - Resource State Coordinator (RSC) with clock controller & genpd provider
>> - Interrupt controller
>> - Power Domain Controller (PDC)
>> - Vendor specific SMMU
>> - SPMI bus arbiter
>> - Top Control and Status Register (TCSR)
>> - Top Level Mode Multiplexer (TLMM)
>> - Debug UART
>> - Reserved memory nodes
>> - Interconnect providers
>> - System timer
>> - UFS
>>
>> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> ---
> 
> [...]
> 
>> +		cpu-map {
>> +			cluster0 {
>> +				core0 {
>> +					cpu = <&cpu0>;
> 
> The values of the MPIDR register (also present in 'reg' of CPU nodes)
> suggest all these CPUs form a single logical cluster
> 
> [...]
> 
>> +		l3: l3-cache {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-unified;
>> +		};
> 
> So far this has been defined as a child of one of the L2 caches, any
> reason for a change?

Look at Monaco and Talos, so you already have exceptions/differences.

The point is that it does not make much sense to be the child of l2.
It's not a child of L2 in the hardware. There is no parent-child
relationship there. You should rather bring argument why claiming L3
cache is a child of L2 because it is rather odd design...

Best regards,
Krzysztof