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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65a3cf38caasm1601501a12.17.2026.02.12.03.59.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Feb 2026 03:59:25 -0800 (PST) Message-ID: <2c2a4e27-fea6-46f5-8d8f-b5869e8dc54b@oss.qualcomm.com> Date: Thu, 12 Feb 2026 12:59:22 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths To: webgeek1234@gmail.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> <20260207-sm8550-ddr-bw-scaling-v1-3-d96c3f39ac4b@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260207-sm8550-ddr-bw-scaling-v1-3-d96c3f39ac4b@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEyMDA4OSBTYWx0ZWRfX9hCJTjuvWaf0 FgIp3Wy4XGdJ8qhDY+i9Hi2asAd/fQtMWE+ohtMLylvPop0AnKsm1oRROXK01XLC6TM9I9jwoT8 O26ziaM4eVi9d6LUYezoUF/9g5TdDLXNHA7y6h9YyUNfnRPivkwmbiHa/2HDT9VXpx5kmrCHPJc SwB4Ys+EEHZTywgvPcJkBc1qBgqLM1avWlhyjYadf36Z5SHgv0oIks/hha6/suNXQHose9imoRt 9/CcPjCfU4GsdkukiMVcPfTa8hpWLizENLQ8LQnzsIrH3iMO18B0g0XMwhK6lFsb+6cGZdKx99b h/Trr+zxQLRxfKRTRRXQo1ru5VcOdv3J39sd22qc9K0x+segGGGKiCcno4sFe/q5DOqsX47coSj LJ68LMxKi5j8wTm32+At1Z1bLM1dVLDYlPF96wwnhJzBx1wSsIHmtlSquywQLnQrZtza6QFHJri etxsj2acVrIAyg0zM/A== X-Proofpoint-GUID: C6IcYHA_uLRomzMq7GmHwTUR-qsPlShE X-Authority-Analysis: v=2.4 cv=Y6j1cxeN c=1 sm=1 tr=0 ts=698dc0a1 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=ze5Wrr8Eh6wvvEUSacsA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: C6IcYHA_uLRomzMq7GmHwTUR-qsPlShE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-12_03,2026-02-11_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602120089 On 2/8/26 2:28 AM, Aaron Kling via B4 Relay wrote: > From: Aaron Kling > > Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) > to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache > frequency by aggregating bandwidth requests of all CPU core with referenc > to the current OPP they are configured in by the LMH/EPSS hardware. > > The effect is a proper caches & DDR frequency scaling when CPU cores > changes frequency. > > The OPP tables were built using the downstream memlat ddr, llcc & l3 > tables for each cluster types with the actual EPSS cpufreq LUT tables > from running a QCS8550 device. > > Signed-off-by: Aaron Kling > --- [...] > + cpu0_opp_table: opp-table-cpu0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-307200000 { > + opp-hz = /bits/ 64 <307200000>; > + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; I think that entries below the first in that memlat table should use the lowest frequency (i.e. if (freq > tbl_entry.min_freq) { vote_for(tbl_entry.bw) }), etc. You can retrieve the list of supported frequencies through debugfs if you apply patch1 from my my in-flight patchset: https://lore.kernel.org/linux-arm-msm/20260108-topic-smem_dramc-v3-0-6b64df58a017@oss.qualcomm.com/ via /sys/kernel/debug/qcom_smem/dram_frequencies Konrad