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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id t1-20020ac25481000000b004d16263b36bsm777310lfk.111.2023.02.17.13.07.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Feb 2023 13:07:06 -0800 (PST) Message-ID: <2e129fd6-d4e5-a955-5355-3ca71166fb33@linaro.org> Date: Fri, 17 Feb 2023 23:07:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH v2 06/14] drm/msm/gpu: Use dev_pm_opp_set_rate for non-GMU GPUs Content-Language: en-GB To: Konrad Dybcio , linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: marijn.suijten@somainline.org, Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Akhil P Oommen , Emma Anholt , Chia-I Wu , Dan Carpenter , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20230214173145.2482651-1-konrad.dybcio@linaro.org> <20230214173145.2482651-7-konrad.dybcio@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230214173145.2482651-7-konrad.dybcio@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 14/02/2023 19:31, Konrad Dybcio wrote: > Currently we only utilize the OPP table connected to the GPU for > getting (available) frequencies. We do however need to scale the > voltage rail(s) accordingly to ensure that we aren't trying to > run the GPU at 1GHz with a VDD_LOW vote, as that would result in > an otherwise inexplainable hang. > > Tell the OPP framework that we want to scale the "core" clock > and swap out the clk_set_rate to a dev_pm_opp_set_rate in > msm_devfreq_target() to enable usage of required-opps and by > extension proper voltage level/corner scaling. > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 ++++ > drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index ce6b76c45b6f..15e405e4f977 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -1047,6 +1047,10 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, > const char *gpu_name; > u32 speedbin; > > + /* This can only be done here, or devm_pm_opp_set_supported_hw will WARN_ON() */ > + if (!IS_ERR(devm_clk_get(dev, "core"))) > + devm_pm_opp_set_clkname(dev, "core"); Can we instead move a call to a6xx_set_supported_hw() / check_speed_bin after the adreno_gpu_init() ? It will call msm_gpu_init, which in turn sets gpu->core_clk. Ideally you can call devm_pm_opp_set_clkname() from that function. Or maybe completely drop gpu->core_clk and always use devm_pm_opp_set_clk_rate(). > + > adreno_gpu->funcs = funcs; > adreno_gpu->info = adreno_info(config->rev); > adreno_gpu->gmem = adreno_gpu->info->gmem; > diff --git a/drivers/gpu/drm/msm/msm_gpu_devfreq.c b/drivers/gpu/drm/msm/msm_gpu_devfreq.c > index e27dbf12b5e8..ea70c1c32d94 100644 > --- a/drivers/gpu/drm/msm/msm_gpu_devfreq.c > +++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c > @@ -48,7 +48,7 @@ static int msm_devfreq_target(struct device *dev, unsigned long *freq, > gpu->funcs->gpu_set_freq(gpu, opp, df->suspended); > mutex_unlock(&df->lock); > } else { > - clk_set_rate(gpu->core_clk, *freq); > + dev_pm_opp_set_rate(dev, *freq); This is not enough, there are calls to clk_set_rate(gpu->core_clk) in msm_gpu.c which are called from the suspend/resume path. > } > > dev_pm_opp_put(opp); -- With best wishes Dmitry