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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5494e52a47asm1295952e87.152.2025.03.04.00.30.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Mar 2025 00:30:25 -0800 (PST) Message-ID: <2e6a0c7e-9c24-42fb-be9a-2b73da8dc69b@linaro.org> Date: Tue, 4 Mar 2025 10:30:14 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc Content-Language: ru-RU To: Dmitry Baryshkov Cc: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Michael Turquette , Stephen Boyd , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> <20250303225521.1780611-3-vladimir.zapolskiy@linaro.org> From: Vladimir Zapolskiy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Dmitry, On 3/4/25 01:53, Dmitry Baryshkov wrote: > On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote: >> SM8550 Camera Clock Controller shall enable both MXC and MMCX power >> domains. > > Are those really required to access the registers of the cammcc? Or is > one of those (MXC?) required to setup PLLs? Also, is this applicable > only to sm8550 or to other similar clock controllers? as it is stated in the cover letter, both power domans shall be on to access CCI or CAMSS. >> >> Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controller") >> Signed-off-by: Vladimir Zapolskiy >> --- >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> index d02d80d731b9..d22b1753d521 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> @@ -3329,7 +3329,8 @@ camcc: clock-controller@ade0000 { >> <&bi_tcxo_div2>, >> <&bi_tcxo_ao_div2>, >> <&sleep_clk>; >> - power-domains = <&rpmhpd SM8550_MMCX>; >> + power-domains = <&rpmhpd SM8550_MXC>, >> + <&rpmhpd SM8550_MMCX>; >> required-opps = <&rpmhpd_opp_low_svs>; >> #clock-cells = <1>; >> #reset-cells = <1>; >> -- >> 2.43.0 >> > -- Best wishes, Vladimir