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Fri, 26 Sep 2025 02:20:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF7rrW7nDK+DSsZ1+iAO+YYBObXr6q47Vhq5ZpJ+PYNdGMhbv2C4q/3UQ6WknVUYLqfgBU/xA== X-Received: by 2002:a17:903:986:b0:26c:9b12:2b6f with SMTP id d9443c01a7336-27ed49b85camr71575355ad.3.1758878438738; Fri, 26 Sep 2025 02:20:38 -0700 (PDT) Received: from [10.217.216.188] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed672aa0asm49116955ad.62.2025.09.26.02.20.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Sep 2025 02:20:38 -0700 (PDT) Message-ID: <2e862560-c422-427e-bace-4199b86d3e6d@oss.qualcomm.com> Date: Fri, 26 Sep 2025 14:50:32 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750 To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20250829-sm8750-videocc-v2-v2-0-4517a5300e41@oss.qualcomm.com> <20250829-sm8750-videocc-v2-v2-3-4517a5300e41@oss.qualcomm.com> <503e1fde-39ea-4107-947b-18b705f2bc51@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <503e1fde-39ea-4107-947b-18b705f2bc51@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 0ZMoV55FO7mDax2V9Azvz9nqRcpv54Gl X-Proofpoint-ORIG-GUID: 0ZMoV55FO7mDax2V9Azvz9nqRcpv54Gl X-Authority-Analysis: v=2.4 cv=api/yCZV c=1 sm=1 tr=0 ts=68d65ae8 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=TyDm9B-wxu7uxzFpS6AA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI1MDE3MSBTYWx0ZWRfX2tfLBPELJNn0 92w3W6zyTtZya/f2jRpnN4HhYuNF+4ZyQFZZnG9mcBCIY3iytwi8/5Wb1dOWCbtLdYlbzZBcYAQ 1v9eTIG27Lh9AyqkyvFZrkr+C/9Gdib0/xcbt57K+iQKKqMYbN10uVRqyzOYsoZ0GcC12fy+kO3 LiYGHeAeGKQFLCd4VE8Wqn0VADvQRjpD31tGN05QY9ldSARAxmnoIco0hf9eO8P+rnQQKJ68xU7 Z6S5fQuWfLoGwu8NLUn+VNYfqxDKgSjvDrJJkBTSI1lVu2vWAWMldrpIwTAn+900MQ9kiJ/OJwT k56rJH5u8jHQzWsXxLN/aMQmPEiQ8JxRXxQvxg5t/JpZs+2omS89Puz9xZsYgKusIobJ4zXy3QR 9hluQ+4qs5XO7j0kUjGMYO5XtzhoaQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-26_02,2025-09-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 adultscore=0 spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509250171 On 9/12/2025 4:38 PM, Konrad Dybcio wrote: > On 8/29/25 12:15 PM, Taniya Das wrote: >> Add support for the video clock controller for video clients to be able >> to request for videocc clocks on SM8750 platform. >> >> Signed-off-by: Taniya Das >> --- > > [...] > >> +static int video_cc_sm8750_probe(struct platform_device *pdev) >> +{ >> + struct regmap *regmap; >> + int ret; >> + >> + ret = devm_pm_runtime_enable(&pdev->dev); >> + if (ret) >> + return ret; >> + >> + ret = pm_runtime_resume_and_get(&pdev->dev); >> + if (ret) >> + return ret; >> + >> + regmap = qcom_cc_map(pdev, &video_cc_sm8750_desc); >> + if (IS_ERR(regmap)) { >> + pm_runtime_put(&pdev->dev); >> + return PTR_ERR(regmap); >> + } >> + >> + clk_taycan_elu_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); >> + >> + /* Update DLY_ACCU_RED_SHIFTER_DONE to 0xF for mvs0, mvs0c */ >> + regmap_update_bits(regmap, 0x8074, 0x1e00000, 0x1e00000); > > regmap_update_bits(..., GENMASK(x, y) /* full field width */, 0xf) Sure, Konrad, will update the change. > > would be easier for the next person to check against docs in case this > needs to ever change or be validated >> + regmap_update_bits(regmap, 0x8040, 0x1e00000, 0x1e00000); >> + >> + regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0)); > > The register description mentions a ticket which I believe says this > is not necessary in production hardware > It is required on production hardware as well. >> + >> + /* >> + * Keep clocks always enabled: >> + * video_cc_ahb_clk >> + * video_cc_sleep_clk >> + * video_cc_xo_clk >> + */ >> + regmap_update_bits(regmap, 0x80a4, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x80f8, BIT(0), BIT(0)); >> + regmap_update_bits(regmap, 0x80d4, BIT(0), BIT(0)); > > Please use the new _desc infra > > Konrad Yes, will migrate to use the _desc infra. -- Thanks, Taniya Das