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Thu, 03 Oct 2024 05:41:48 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4935fi0u026004 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 3 Oct 2024 05:41:44 GMT Received: from [10.214.67.37] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 2 Oct 2024 22:41:40 -0700 Message-ID: <2ecaa16e-e0ec-44af-8a0f-438dc25ca4c1@quicinc.com> Date: Thu, 3 Oct 2024 11:11:27 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: qcom: sc7280: Add cpucp mbox node To: Krzysztof Kozlowski , Sibi Sankar , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , Bjorn Andersson , Konrad Dybcio CC: , , , Ramakrishna Gottimukkula References: <20240924050941.1251485-1-quic_kshivnan@quicinc.com> <20240924050941.1251485-4-quic_kshivnan@quicinc.com> Content-Language: en-US From: Shivnandan Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PNO3YNqZ7E57y4vz9SLZf_ri_kLqPaE8 X-Proofpoint-ORIG-GUID: PNO3YNqZ7E57y4vz9SLZf_ri_kLqPaE8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 phishscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2410030037 On 9/25/2024 7:52 PM, Krzysztof Kozlowski wrote: > On 24/09/2024 07:09, Shivnandan Kumar wrote: >> Add the CPUCP mailbox node required for communication with CPUCP. >> >> Signed-off-by: Shivnandan Kumar >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 3d8410683402..4b9b26a75c62 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -4009,6 +4009,14 @@ gem_noc: interconnect@9100000 { >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + cpucp_mbox: mailbox@17430000 { > > Are you sure you placed it in correct location (the order is by unit > address, see DTS coding style). > I will correct it in next series. >> + compatible = "qcom,sc7280-cpucp-mbox"; >> + reg = <0 0x18590000 0 0x2000>, >> + <0 0x17C00000 0 0x10>; > > Lowercase hex... we just fixed it everywhere and you introduce again > same issues. > ACK > > > Best regards, > Krzysztof >