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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b942f18902bsm477819166b.61.2026.03.10.06.33.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Mar 2026 06:33:28 -0700 (PDT) Message-ID: <2f4f298c-5fc0-46e6-a1bb-4c37c21786da@oss.qualcomm.com> Date: Tue, 10 Mar 2026 14:33:25 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes To: Akhil P Oommen , Taniya Das Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio References: <20260305-gpucc_sm8750_v2-v5-0-78292b40b053@oss.qualcomm.com> <20260305-gpucc_sm8750_v2-v5-3-78292b40b053@oss.qualcomm.com> <67922413-af8d-4e75-aa49-079889576a73@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <67922413-af8d-4e75-aa49-079889576a73@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDExOCBTYWx0ZWRfX+69AKM6D1En8 WtktNkRmu0iUTRj8rzXGJ3Q8PyZaNekS5oFxTHVtdsWL/diBmMgCpX0pxdbBT70G28O3zIbsuT9 RZC/6bJb0L22zu+qiltroX2Aml5aSMzYXS3BfjKbfoGOhJpDI+pVsYZoNfGDgrsjxKKAYk5cNLe KYh6XrSOemL9fjaTStS3D5e+CupJ/43Tx8+Q7RkBt+keD+T4eTR2lXtP04YaceZL/oBY+nLc1a9 IJ8qovY38+Tbp1Fgxrd3bRqr6fEVDoeWli+MoDTd21b4rZeJANqazBMCTlFsQWNf8NdS4fxtLEG BPeMpkTsWoeEr8HG/LHaG0LdrhjEkM2iP1gLsKjFP0zwA3HJNIGX16JWI0QbuzcBtIaWCq8AEFM ZucYYeVsAzVEc8B3gpLDcbarz3fuFaoyDn4wBfA9g5q5L5T4xBC5N3qcDla48lDi5UPfUzN/mpT MxrggOh4jPoqkVY6VUw== X-Proofpoint-GUID: f_pKFQuT3DxOcnZPbs8tPHIJ52rhWt2h X-Authority-Analysis: v=2.4 cv=KLxXzVFo c=1 sm=1 tr=0 ts=69b01daa cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=6F_KMvjuWJjJSnLB6NgA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: f_pKFQuT3DxOcnZPbs8tPHIJ52rhWt2h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_02,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100118 On 3/6/26 10:40 AM, Akhil P Oommen wrote: > On 3/5/2026 4:10 PM, Taniya Das wrote: >> From: Konrad Dybcio >> >> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this >> is simply a separate block housing the GX GDSC) nodes, required to >> power up the graphics-related hardware. >> >> Make use of it by enabling the associated IOMMU as well. The GPU itself >> needs some more work and will be enabled later. >> >> Reviewed-by: Abel Vesa >> Signed-off-by: Konrad Dybcio >> Co-developed-by: Taniya Das >> Signed-off-by: Taniya Das >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 68 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726dc6279078c21c 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -4,7 +4,9 @@ >> */ >> >> #include >> +#include >> #include >> +#include >> #include >> #include >> #include >> @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 { >> #power-domain-cells = <1>; >> }; >> >> + gxclkctl: clock-controller@3d64000 { >> + compatible = "qcom,sm8750-gxclkctl"; >> + reg = <0x0 0x03d64000 0x0 0x6000>; >> + >> + power-domains = <&rpmhpd RPMHPD_GFX>, >> + <&rpmhpd RPMHPD_GMXC>, >> + <&gpucc GPU_CC_CX_GDSC>; >> + >> + #power-domain-cells = <1>; >> + }; >> + >> + gpucc: clock-controller@3d90000 { >> + compatible = "qcom,sm8750-gpucc"; >> + reg = <0x0 0x03d90000 0x0 0x9800>; >> + >> + clocks = <&bi_tcxo_div2>, >> + <&gcc GCC_GPU_GPLL0_CLK_SRC>, >> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; >> + >> + power-domains = <&rpmhpd RPMHPD_MX>, >> + <&rpmhpd RPMHPD_CX>; >> + required-opps = <&rpmhpd_opp_low_svs>, >> + <&rpmhpd_opp_low_svs>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> pdc: interrupt-controller@b220000 { >> compatible = "qcom,sm8750-pdc", "qcom,pdc"; >> reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; >> @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint { >> }; >> }; >> >> + adreno_smmu: iommu@3da0000 { > > Should we move this node right after the gpucc node to sort based on > address? Yes, this might have been a rebase artifact Konrad