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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab7d5f84968sm66674366b.164.2025.02.10.11.14.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 11:14:25 -0800 (PST) Message-ID: <32b02433-bf2a-4f22-afb3-485bcef4f85d@oss.qualcomm.com> Date: Mon, 10 Feb 2025 20:14:22 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller To: Sricharan Ramabadhran , Konrad Dybcio , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Dmitry Baryshkov References: <20250127093128.2611247-1-quic_srichara@quicinc.com> <20250127093128.2611247-3-quic_srichara@quicinc.com> <47f7553d-74a2-4da0-a64c-cc49a2170efb@oss.qualcomm.com> <123a324c-561a-4081-be43-8d8ed0662acc@quicinc.com> <6c8bb178-1758-4b73-bbaf-8572dc1216d3@oss.qualcomm.com> <7031f2da-36bb-4655-a4df-fa85c99e6eb4@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <7031f2da-36bb-4655-a4df-fa85c99e6eb4@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: hZp5XXAFS6Mt0EJ_IMW3_FKjO1fdlSlG X-Proofpoint-ORIG-GUID: hZp5XXAFS6Mt0EJ_IMW3_FKjO1fdlSlG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-10_10,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502100154 On 4.02.2025 7:28 AM, Sricharan Ramabadhran wrote: > > > On 2/1/2025 8:55 PM, Konrad Dybcio wrote: >> On 30.01.2025 11:03 AM, Sricharan Ramabadhran wrote: >>> >>> >>> On 1/28/2025 5:29 PM, Konrad Dybcio wrote: >>>> On 27.01.2025 10:31 AM, Sricharan R wrote: >>>>> From: Sricharan Ramabadhran >>>>> >>>>> CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. >>>>> Add support for the APSS PLL, RCG and clock enable for ipq5424. >>>>> The PLL, RCG register space are clubbed. Hence adding new APSS driver >>>>> for both PLL and RCG/CBC control. Also the L3 cache has a separate pll >>>>> and needs to be scaled along with the CPU. >>>>> >>>>> Co-developed-by: Md Sadre Alam >>>>> Signed-off-by: Md Sadre Alam >>>>> Signed-off-by: Sricharan Ramabadhran >>>>> --- >> >> [...] >> >>>>> +    clk_alpha_pll_configure(&ipq5424_l3_pll, regmap, &l3_pll_config); >>>>> + >>>>> +    clk_alpha_pll_configure(&ipq5424_apss_pll, regmap, &apss_pll_config); >>>>> + >>>>> +    ret = qcom_cc_really_probe(dev, &apss_ipq5424_desc, regmap); >>>>> +    if (ret) >>>>> +        return ret; >>>>> + >>>>> +    dev_dbg(&pdev->dev, "Registered APSS & L3 clock provider\n"); >>>>> + >>>>> +    apss_ipq5424_cfg->dev = dev; >>>>> +    apss_ipq5424_cfg->hw = &apss_silver_clk_src.clkr.hw; >>>>> +    apss_ipq5424_cfg->cpu_clk_notifier.notifier_call = cpu_clk_notifier_fn; >>>>> + >>>>> +    apss_ipq5424_cfg->l3_clk = clk_hw_get_clk(&l3_core_clk.clkr.hw, "l3_clk"); >>>>> +    if (IS_ERR(apss_ipq5424_cfg->l3_clk)) { >>>>> +        dev_err(&pdev->dev, "Failed to get L3 clk, %ld\n", >>>>> +            PTR_ERR(apss_ipq5424_cfg->l3_clk)); >>>>> +        return PTR_ERR(apss_ipq5424_cfg->l3_clk); >>>>> +    } >>>> >>>> Now that you'll use OPP, you can drop all this getting.. maybe even the >>>> apss_ipq5424_cfg struct could be let go >>> >>> ok, is the suggestion here to use devm_pm_opp_set_config ? >> >> Since what you tried to do here is binding CPU and L3 frequencies together, >> yeah, we can just scale two clocks from OPP. >> >> On some newer platforms using the epss-l3 driver, or on msm8996 with a more >> complex setup, we expose the L3 voter as an interconnect, but here it would >> seem that we directly control the clock that feeds it. > > ok, will update and check. +Dmitry Giving it yet another thought, we now have infrastructure in clk/qcom/common.c to register icc clocks. We can register the L3 one as such and make the description like: cpu0: cpu@0 { [...] interconnects = <&apss L3_CLK>; [...] }; cpu_opp_table: opp-table { opp-1234000 { opp-hz = /bits/ 64 <1234000>; opp-peak-kBps = ; }; }; as that will both match how we modeled msm8996 & require less code changes Dmitry, Bjorn? Konrad