From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: "Jyothi Kumar Seerapu" <quic_jseerapu@quicinc.com>,
"Vinod Koul" <vkoul@kernel.org>, "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>,
"Andi Shyti" <andi.shyti@kernel.org>,
"Sumit Semwal" <sumit.semwal@linaro.org>,
"Christian König" <christian.koenig@amd.com>
Cc: cros-qcom-dts-watchers@chromium.org,
linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-i2c@vger.kernel.org, linux-media@vger.kernel.org,
dri-devel@lists.freedesktop.org, linaro-mm-sig@lists.linaro.org,
quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com
Subject: Re: [PATCH v1 3/5] dmaengine: qcom: gpi: Add provision to support TRE size as the fourth argument of dma-cells property
Date: Fri, 25 Oct 2024 20:17:03 +0200 [thread overview]
Message-ID: <333948f0-44ff-424a-8d38-5fba719d2aeb@oss.qualcomm.com> (raw)
In-Reply-To: <20241015120750.21217-4-quic_jseerapu@quicinc.com>
On 15.10.2024 2:07 PM, Jyothi Kumar Seerapu wrote:
> The current GPI driver hardcodes the channel TRE (Transfer Ring Element)
> size to 64. For scenarios requiring high performance with multiple
> messages in a transfer, use Block Event Interrupt (BEI).
> This method triggers interrupt after specific message transfers and
> the last message transfer, effectively reducing the number of interrupts.
> For multiple transfers utilizing BEI, a channel TRE size of 64 is
> insufficient and may lead to transfer failures, indicated by errors
> related to unavailable memory space.
>
> Added provision to modify the channel TRE size via the device tree.
> The Default channel TRE size is set to 64, but this value can update
> in the device tree which will then be parsed by the GPI driver.
>
> Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
> ---
1. Is the total memory pool for these shared?
2. Is there any scenario where we want TRE size to be lower and
not higher? Are there any drawbacks to always keeping them at
SOME_MAX_VALUE?
3. Is this something we should configure at boot time (in firmware)?
Perhaps this could be decided based on client device settings (which
may or may not require adding some field in the i2c framework)
Konrad
next prev parent reply other threads:[~2024-10-25 18:17 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 12:07 [PATCH v1 0/5] Add Block event interrupt support for I2C protocol Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property Jyothi Kumar Seerapu
2024-10-15 13:26 ` Rob Herring (Arm)
2024-10-28 5:57 ` Jyothi Kumar Seerapu
2024-10-15 13:31 ` Krzysztof Kozlowski
2024-10-25 18:11 ` Jyothi Kumar Seerapu
2024-10-15 14:01 ` Rob Herring
2024-10-28 5:38 ` Jyothi Kumar Seerapu
2024-10-16 4:54 ` Vinod Koul
2024-10-25 18:25 ` Jyothi Kumar Seerapu
2024-10-28 5:50 ` Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size Jyothi Kumar Seerapu
2024-10-15 13:33 ` Krzysztof Kozlowski
2024-10-16 14:35 ` Bjorn Andersson
2024-10-17 7:10 ` Krzysztof Kozlowski
2024-10-28 5:34 ` Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 3/5] dmaengine: qcom: gpi: Add provision to support TRE size as the fourth argument of dma-cells property Jyothi Kumar Seerapu
2024-10-25 18:17 ` Konrad Dybcio [this message]
2024-10-28 6:32 ` Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 4/5] dmaengine: qcom: gpi: Add GPI Block event interrupt support Jyothi Kumar Seerapu
2024-10-15 12:07 ` [PATCH v1 5/5] i2c: i2c-qcom-geni: Add " Jyothi Kumar Seerapu
2024-10-16 15:06 ` Andi Shyti
2024-10-28 6:04 ` Jyothi Kumar Seerapu
2024-10-18 22:11 ` kernel test robot
2024-10-28 6:07 ` Jyothi Kumar Seerapu
2024-10-19 3:12 ` kernel test robot
2024-10-28 6:06 ` Jyothi Kumar Seerapu
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