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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8e9d2f9asm33111087b3a.19.2026.04.27.00.39.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Apr 2026 00:39:07 -0700 (PDT) Message-ID: <337789c5-7311-4613-9daf-915fcae0c6fc@oss.qualcomm.com> Date: Mon, 27 Apr 2026 15:39:02 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks To: Yingchao Deng , Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_yingdeng@quicinc.com, Jinlong Mao , Tingwei Zhang References: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> <20260426-extended-cti-v8-3-23b900a4902f@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20260426-extended-cti-v8-3-23b900a4902f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ANHlHo2fUemWkhq6ONeXwIXjCqaeHXMk X-Proofpoint-ORIG-GUID: ANHlHo2fUemWkhq6ONeXwIXjCqaeHXMk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDA4MCBTYWx0ZWRfXzZPpfGiavs4k cHwzemx6WuW/bnxBwWid1uLzZOVEM3ik7oQDoXEGvLL37ZZ1uz/9SFkehBDzkukDqegPqZLyREx gWGV5DoqM8hSijx5e5FpgZKl9KjY8uIz73b2QdgkYYjKeIO7r2+x+16haH6mn7x7JBNxoWhGEwK LKtmM5mKncZtROGWEQjwWBNhsXZw74nqVAU3eN3HvF77NNDeZJMhDdnhRZSJM70IouQz6zJhdLR ouvmkYpJuaP5VPsWeFN0ysedLAnaBQUQ+oazu6Uwx3DFPqMnFmguOYbhUo+VVGob6a8nODnCndn OBdQWyHXqcFVjj4Jt/BvOBgj+GXm6EuyOL6vXsMk6qi2WTazlis8IjfeTuUrz9rgkC24kESQyOB E6VK4NujZQjgDE6LXi1R6tvYXX0lTyUYgKhzUqjG/5XS2zUEJgEGM3fXNV8wQSfM6Rt2WZ8kfYe 9/h/n6eeGQ5PetSM1kQ== X-Authority-Analysis: v=2.4 cv=FM8rAeos c=1 sm=1 tr=0 ts=69ef129d cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=Fi1y-F4gZlMYRSbziuEA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-27_02,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 bulkscore=0 phishscore=0 spamscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270080 On 4/26/2026 5:44 PM, Yingchao Deng wrote: > Qualcomm implements an extended variant of the ARM CoreSight CTI with a > different register layout and vendor-specific behavior. While the > programming model remains largely compatible, the register offsets differ > from the standard ARM CTI and require explicit handling. > > Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI > driver data. Introduce a small mapping layer to translate standard CTI > register offsets to Qualcomm-specific offsets, allowing the rest of the > driver to use a common register access path. > > Additionally, handle a Qualcomm-specific quirk where the CLAIMSET > register is incorrectly initialized to a non-zero value, which can cause > tools or drivers to assume the component is already claimed. Clear the > register during probe to reflect the actual unclaimed state. > > No functional change is intended for standard ARM CTI devices. > > Co-developed-by: Jinlong Mao > Signed-off-by: Jinlong Mao > Signed-off-by: Yingchao Deng > --- > drivers/hwtracing/coresight/coresight-cti-core.c | 28 +++++++++- > drivers/hwtracing/coresight/coresight-cti.h | 4 +- > drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++++++++++++++ > 3 files changed, 95 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c > index c4cbeb64365b..b1c69a3e9b99 100644 > --- a/drivers/hwtracing/coresight/coresight-cti-core.c > +++ b/drivers/hwtracing/coresight/coresight-cti-core.c > @@ -21,6 +21,7 @@ > > #include "coresight-priv.h" > #include "coresight-cti.h" > +#include "qcom-cti.h" > > /* > * CTI devices can be associated with a PE, or be connected to CoreSight > @@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg) > u32 offset = CTI_REG_CLR_NR(reg); > u32 nr = CTI_REG_GET_NR(reg); > > + /* convert to qcom specific offset */ > + if (unlikely(drvdata->is_qcom_cti)) I prefer to drop the unlikely here, let the cpu do the branch predictor. > + offset = cti_qcom_reg_off(offset); > + > return drvdata->base + offset + sizeof(u32) * nr; > } > > @@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32 ackval) > /* DEVID[19:16] - number of CTM channels */ > #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) > > +/* DEVARCH[31:21] - ARCHITECT */ > +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31)) > + > static int cti_set_default_config(struct device *dev, > struct cti_drvdata *drvdata) > { > @@ -700,6 +708,7 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > struct coresight_desc cti_desc; > struct coresight_platform_data *pdata = NULL; > struct resource *res = &adev->res; > + u32 devarch; > > /* driver data*/ > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > @@ -724,6 +733,22 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > > raw_spin_lock_init(&drvdata->spinlock); > > + devarch = readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); > + if (CTI_DEVARCH_ARCHITECT(devarch) == ARCHITECT_QCOM) { > + drvdata->is_qcom_cti = true; > + /* > + * QCOM CTI does not implement Claimtag functionality as > + * per CoreSight specification, but its CLAIMSET register > + * is incorrectly initialized to 0xF. This can mislead > + * tools or drivers into thinking the component is claimed. > + * > + * Reset CLAIMSET to 0 to reflect that no claims are active. > + */ > + CS_UNLOCK(drvdata->base); > + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); > + CS_LOCK(drvdata->base); > + } > + > /* initialise CTI driver config values */ > ret = cti_set_default_config(dev, drvdata); > if (ret) > @@ -780,7 +805,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id) > > /* all done - dec pm refcount */ > pm_runtime_put(&adev->dev); > - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); > + dev_info(&drvdata->csdev->dev, > + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); > return 0; > } > > diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h > index dd1ba44518c4..2598601e7b93 100644 > --- a/drivers/hwtracing/coresight/coresight-cti.h > +++ b/drivers/hwtracing/coresight/coresight-cti.h > @@ -55,10 +55,11 @@ struct fwnode_handle; > /* > * CTI CSSoc 600 has a max of 32 trigger signals per direction. > * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. > + * QCOM CTI supports up to 128 trigger signals per direction. > * Max of in and out defined in the DEVID register. > * - pick up actual number used from .dts parameters if present. > */ > -#define CTIINOUTEN_MAX 32 > +#define CTIINOUTEN_MAX 128 > > /* > * Encode CTI register offset and register index in one u32: > @@ -188,6 +189,7 @@ struct cti_drvdata { > raw_spinlock_t spinlock; > struct cti_config config; > struct list_head node; > + bool is_qcom_cti; missed document. Thanks, Jie > }; > > /* > diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/coresight/qcom-cti.h > new file mode 100644 > index 000000000000..fd1bf07d7cb4 > --- /dev/null > +++ b/drivers/hwtracing/coresight/qcom-cti.h > @@ -0,0 +1,65 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef _CORESIGHT_QCOM_CTI_H > +#define _CORESIGHT_QCOM_CTI_H > + > +#include "coresight-cti.h" > + > +#define ARCHITECT_QCOM 0x477 > + > +/* CTI programming registers */ > +#define QCOM_CTIINTACK 0x020 > +#define QCOM_CTIAPPSET 0x004 > +#define QCOM_CTIAPPCLEAR 0x008 > +#define QCOM_CTIAPPPULSE 0x00C > +#define QCOM_CTIINEN 0x400 > +#define QCOM_CTIOUTEN 0x800 > +#define QCOM_CTITRIGINSTATUS 0x040 > +#define QCOM_CTITRIGOUTSTATUS 0x060 > +#define QCOM_CTICHINSTATUS 0x080 > +#define QCOM_CTICHOUTSTATUS 0x084 > +#define QCOM_CTIGATE 0x088 > +#define QCOM_ASICCTL 0x08C > +/* Integration test registers */ > +#define QCOM_ITCHINACK 0xE70 > +#define QCOM_ITTRIGINACK 0xE80 > +#define QCOM_ITCHOUT 0xE74 > +#define QCOM_ITTRIGOUT 0xEA0 > +#define QCOM_ITCHOUTACK 0xE78 > +#define QCOM_ITTRIGOUTACK 0xEC0 > +#define QCOM_ITCHIN 0xE7C > +#define QCOM_ITTRIGIN 0xEE0 > + > +static noinline u32 cti_qcom_reg_off(u32 offset) > +{ > + switch (offset) { > + case CTIINTACK: return QCOM_CTIINTACK; > + case CTIAPPSET: return QCOM_CTIAPPSET; > + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; > + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; > + case CTIINEN: return QCOM_CTIINEN; > + case CTIOUTEN: return QCOM_CTIOUTEN; > + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; > + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; > + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; > + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; > + case CTIGATE: return QCOM_CTIGATE; > + case ASICCTL: return QCOM_ASICCTL; > + case ITCHINACK: return QCOM_ITCHINACK; > + case ITTRIGINACK: return QCOM_ITTRIGINACK; > + case ITCHOUT: return QCOM_ITCHOUT; > + case ITTRIGOUT: return QCOM_ITTRIGOUT; > + case ITCHOUTACK: return QCOM_ITCHOUTACK; > + case ITTRIGOUTACK: return QCOM_ITTRIGOUTACK; > + case ITCHIN: return QCOM_ITCHIN; > + case ITTRIGIN: return QCOM_ITTRIGIN; > + > + default: > + return offset; > + } > +} > + > +#endif /* _CORESIGHT_QCOM_CTI_H */ >