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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id c3-20020ac25f63000000b0049f54c5f2a4sm2894980lfc.229.2023.01.11.12.59.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 12:59:26 -0800 (PST) Message-ID: <33a6bf2c-bb93-c183-3915-5b90b72e4503@linaro.org> Date: Wed, 11 Jan 2023 21:59:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 04/13] clk: qcom: cpu-8996: support using GPLL0 as SMUX input Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20230111192004.2509750-1-dmitry.baryshkov@linaro.org> <20230111192004.2509750-5-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20230111192004.2509750-5-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 11.01.2023 20:19, Dmitry Baryshkov wrote: > In some cases the driver might need using GPLL0 to drive CPU clocks. > Bring it in through the sys_apcs_aux clock. > > Signed-off-by: Dmitry Baryshkov > --- Oh that's new.. downstream doesn't talk about this.. Konrad > drivers/clk/qcom/clk-cpu-8996.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c > index d51965fda56d..0e0c00d44c6f 100644 > --- a/drivers/clk/qcom/clk-cpu-8996.c > +++ b/drivers/clk/qcom/clk-cpu-8996.c > @@ -12,6 +12,8 @@ > * +-------+ > * XO | | > * +------------------>0 | > + * SYS_APCS_AUX | | > + * +------------------>3 | > * | | > * PLL/2 | SMUX +----+ > * +------->1 | | > @@ -310,20 +312,29 @@ static const struct clk_ops clk_cpu_8996_pmux_ops = { > .determine_rate = clk_cpu_8996_pmux_determine_rate, > }; > > +static const struct parent_map smux_parent_map[] = { > + { .cfg = 0, }, /* xo */ > + { .cfg = 1, }, /* pll */ > + { .cfg = 3, }, /* sys_apcs_aux */ > +}; > + > static const struct clk_parent_data pwrcl_smux_parents[] = { > { .fw_name = "xo" }, > { .hw = &pwrcl_pll_postdiv.hw }, > + { .fw_name = "sys_apcs_aux" }, > }; > > static const struct clk_parent_data perfcl_smux_parents[] = { > { .fw_name = "xo" }, > { .hw = &perfcl_pll_postdiv.hw }, > + { .fw_name = "sys_apcs_aux" }, > }; > > static struct clk_regmap_mux pwrcl_smux = { > .reg = PWRCL_REG_OFFSET + MUX_OFFSET, > .shift = 2, > .width = 2, > + .parent_map = smux_parent_map, > .clkr.hw.init = &(struct clk_init_data) { > .name = "pwrcl_smux", > .parent_data = pwrcl_smux_parents, > @@ -337,6 +348,7 @@ static struct clk_regmap_mux perfcl_smux = { > .reg = PERFCL_REG_OFFSET + MUX_OFFSET, > .shift = 2, > .width = 2, > + .parent_map = smux_parent_map, > .clkr.hw.init = &(struct clk_init_data) { > .name = "perfcl_smux", > .parent_data = perfcl_smux_parents,