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Sat, 09 May 2026 09:58:10 -0700 (PDT) X-Received: by 2002:a17:90b:5603:b0:366:479c:59de with SMTP id 98e67ed59e1d1-366479c5db9mr8171370a91.8.1778345889474; Sat, 09 May 2026 09:58:09 -0700 (PDT) Received: from [192.168.0.9] ([49.205.255.40]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1e35632sm58541735ad.53.2026.05.09.09.58.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 09 May 2026 09:58:08 -0700 (PDT) Message-ID: <34962003-c54c-a64a-2846-8f741fec5802@oss.qualcomm.com> Date: Sat, 9 May 2026 22:26:49 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 From: Vishnu Reddy Subject: Re: [PATCH v5 13/14] arm64: dts: qcom: glymur: Add iris video node To: Dmitry Baryshkov Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Joerg Roedel , Will Deacon , Robin Murphy , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Jorge Ramirez-Ortiz , Del Regno , Bjorn Andersson , Konrad Dybcio , linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, Krzysztof Kozlowski , devicetree@vger.kernel.org References: <20260509-glymur-v5-0-7fbb340c5dbd@oss.qualcomm.com> <20260509-glymur-v5-13-7fbb340c5dbd@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: ZzajsuO6OUxdYGdhQQdlGcLlUztvYBVM X-Authority-Analysis: v=2.4 cv=asaCzyZV c=1 sm=1 tr=0 ts=69ff67a3 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=SpcZ+gRb+6o1zy8jT5J+bQ==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=tcww-dwagKCKl4DpuMYA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: ZzajsuO6OUxdYGdhQQdlGcLlUztvYBVM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA5MDE4NCBTYWx0ZWRfX4C6Avxp7qzh3 0ZO1BTmpirn01an2rj2PzmIMR+0j65yovwwEHrYOAFdlYJo3Fjy51+vb2v+DZnTR1koLckFGaHS AczmeOZUtnBGjm5R16MSGR7TnosUYvuSAprWF6pISJeWCAIjuBQ4rNEYrBiTgmrCzysov0MswFB PLIXVcalUxvh+NczQDWnQDbcooXELtB8aE4TfwjuI30l2gZ10EtxFw5dD6icFI2waZr+sVJaOi/ 4v9WxcnlbwsyFmvqtp0j4Vtyt+b0w+x7064tcPJINcBd7fk4TGA7CPkOstOB8yXc5PFyDaMmTTQ QHiRW2JCDfUrzJUhuaq6gLgPZJICgabkxMKQipoWXfHfx20EkZWz5sixd3gw2sAiK2qf1iQikI+ IFgEq5LE3yI44vpvDhUPUtgGmrW0bMDQ1siDJrD6hTFaQvtLpx0P1t2dkdR6AABexVLQOs1OQwM wUZlXOXjguuzLwXLB+w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-09_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605090184 On 5/9/2026 12:57 AM, Dmitry Baryshkov wrote: > On Sat, May 09, 2026 at 12:30:02AM +0530, Vishnu Reddy wrote: >> Add iris video codec to glymur SoC, which comes with significantly >> different powering up sequence than previous platforms, thus different >> clocks and resets. >> >> Reviewed-by: Vikash Garodia >> Signed-off-by: Vishnu Reddy >> --- >> arch/arm64/boot/dts/qcom/glymur.dtsi | 118 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 118 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >> index f23cf81ddb77..c47443174f97 100644 >> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi >> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >> @@ -13,6 +13,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -4163,6 +4164,123 @@ usb_mp: usb@a400000 { >> status = "disabled"; >> }; >> >> + iris: video-codec@aa00000 { >> + compatible = "qcom,glymur-iris"; >> + reg = <0x0 0xaa00000 0x0 0xf0000>; >> + >> + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, >> + <&videocc VIDEO_CC_MVS0C_CLK>, >> + <&videocc VIDEO_CC_MVS0_CLK>, >> + <&gcc GCC_VIDEO_AXI0C_CLK>, >> + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, >> + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, >> + <&gcc GCC_VIDEO_AXI1_CLK>, >> + <&videocc VIDEO_CC_MVS1_CLK>, >> + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; >> + clock-names = "iface", >> + "core", >> + "vcodec0_core", >> + "iface1", > I first wrote the comment regarding resets. But the clocks seem to have > the same pattern. It's not just "iface1" clock. It's the clock for one > of the cores. And there is another clock for another core. Please make > that nicely named. In v1, I used iface_ctrl to reflect the clock purpose, but received the feedback [1] to align with the iface1 naming convention used on earlier platforms. [1] https://lore.kernel.org/all/20260414-lush-reindeer-of-storm-bbe918@quoll/ >> + "core_freerun", >> + "vcodec0_core_freerun", >> + "iface2", >> + "vcodec1_core", >> + "vcodec1_core_freerun"; >> + >> + dma-coherent; >> + >> + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, >> + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "cpu-cfg", >> + "video-mem"; >> + >> + interrupts = ; >> + >> + iommus = <&apps_smmu 0x1940 0x0>, >> + <&apps_smmu 0x1943 0x0>, >> + <&apps_smmu 0x1944 0x0>, >> + <&apps_smmu 0x19e0 0x0>; >> + >> + iommu-map = ; >> + >> + memory-region = <&video_mem>; >> + >> + operating-points-v2 = <&iris_opp_table>; >> + >> + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, >> + <&videocc VIDEO_CC_MVS0_GDSC>, >> + <&rpmhpd RPMHPD_MXC>, >> + <&rpmhpd RPMHPD_MMCX>, >> + <&videocc VIDEO_CC_MVS1_GDSC>; >> + power-domain-names = "venus", >> + "vcodec0", >> + "mxc", >> + "mmcx", >> + "vcodec1"; >> + >> + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, >> + <&gcc GCC_VIDEO_AXI0C_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, >> + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; >> + reset-names = "bus0", >> + "bus1", > The names of the resets suggest that there is single "common" reset and > then one reset per each core. Two resets for controller and two resets for each per vcodec core. >> + "core", >> + "vcodec0_core", >> + "bus2", >> + "vcodec1_core"; > Are there two codecs? Or are there two cores? Your naming suggests the > former case. Two vcodec cores. >> + >> + /* >> + * IRIS firmware is signed by vendors, only >> + * enable on boards where the proper signed firmware >> + * is available. >> + */ >> + status = "disabled"; >> + >> + iris_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-240000000 { >> + opp-hz = /bits/ 64 <240000000 240000000 360000000>; >> + required-opps = <&rpmhpd_opp_svs>, >> + <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-338000000 { >> + opp-hz = /bits/ 64 <338000000 338000000 507000000>; >> + required-opps = <&rpmhpd_opp_svs>, >> + <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-366000000 { >> + opp-hz = /bits/ 64 <366000000 366000000 549000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-444000000 { >> + opp-hz = /bits/ 64 <444000000 444000000 666000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_nom>; >> + }; >> + >> + opp-533333334 { >> + opp-hz = /bits/ 64 <533333334 533333334 800000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_turbo>; >> + }; >> + >> + opp-655000000 { >> + opp-hz = /bits/ 64 <655000000 655000000 982000000>; >> + required-opps = <&rpmhpd_opp_nom>, >> + <&rpmhpd_opp_turbo_l1>; >> + }; >> + }; >> + }; >> + >> mdss: display-subsystem@ae00000 { >> compatible = "qcom,glymur-mdss"; >> reg = <0x0 0x0ae00000 0x0 0x1000>; >> >> -- >> 2.34.1 >>