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Tue, 15 Feb 2022 05:42:08 -0800 (PST) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x6sm4522430lfu.48.2022.02.15.05.42.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Feb 2022 05:42:08 -0800 (PST) Message-ID: <34f2eea3-c486-87ff-668d-7191b59c7d6f@linaro.org> Date: Tue, 15 Feb 2022 16:42:07 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH v2 1/2] drm/msm/dpu: Add INTF_5 interrupts Content-Language: en-GB To: Bjorn Andersson , Rob Clark , Abhinav Kumar Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20220215043353.1256754-1-bjorn.andersson@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20220215043353.1256754-1-bjorn.andersson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 15/02/2022 07:33, Bjorn Andersson wrote: > SC8180x has the eDP controller wired up to INTF_5, so add the interrupt > register block for this interface to the list. > > Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov > --- > > Changes since v1: > - None > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 6 ++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index a77a5eaa78ad..dd2161e7bdb6 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -23,6 +23,7 @@ > #define MDP_INTF_2_OFF 0x6B000 > #define MDP_INTF_3_OFF 0x6B800 > #define MDP_INTF_4_OFF 0x6C000 > +#define MDP_INTF_5_OFF 0x6C800 > #define MDP_AD4_0_OFF 0x7C000 > #define MDP_AD4_1_OFF 0x7D000 > #define MDP_AD4_INTR_EN_OFF 0x41c > @@ -93,6 +94,11 @@ static const struct dpu_intr_reg dpu_intr_set[] = { > MDP_INTF_4_OFF+INTF_INTR_EN, > MDP_INTF_4_OFF+INTF_INTR_STATUS > }, > + { > + MDP_INTF_5_OFF+INTF_INTR_CLEAR, > + MDP_INTF_5_OFF+INTF_INTR_EN, > + MDP_INTF_5_OFF+INTF_INTR_STATUS > + }, > { > MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF, > MDP_AD4_0_OFF + MDP_AD4_INTR_EN_OFF, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > index 1ab75cccd145..37379966d8ec 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h > @@ -22,6 +22,7 @@ enum dpu_hw_intr_reg { > MDP_INTF2_INTR, > MDP_INTF3_INTR, > MDP_INTF4_INTR, > + MDP_INTF5_INTR, > MDP_AD4_0_INTR, > MDP_AD4_1_INTR, > MDP_INTF0_7xxx_INTR, -- With best wishes Dmitry