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Mon, 25 Nov 2024 03:22:11 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AP3MAuf001389 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 03:22:10 GMT Received: from [10.253.38.8] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 24 Nov 2024 19:22:06 -0800 Message-ID: <34ff9c8a-f288-4f76-be22-a1c784c24d2f@quicinc.com> Date: Mon, 25 Nov 2024 11:22:02 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/2] arm64: dts: qcom: qcs8300: add the first 2.5G ethernet To: Andrew Lunn CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , , , , References: <20241123-dts_qcs8300-v4-0-b10b8ac634a9@quicinc.com> <20241123-dts_qcs8300-v4-1-b10b8ac634a9@quicinc.com> <355ff08c-d0a8-49e7-8afc-2e4adddf2c9e@lunn.ch> Content-Language: en-US From: Yijie Yang In-Reply-To: <355ff08c-d0a8-49e7-8afc-2e4adddf2c9e@lunn.ch> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TTcvx6yjmz1Zg6OGHlL2EH7Xvn4wwEiD X-Proofpoint-ORIG-GUID: TTcvx6yjmz1Zg6OGHlL2EH7Xvn4wwEiD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxlogscore=804 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250027 On 2024-11-24 03:36, Andrew Lunn wrote: >> + ethernet0: ethernet@23040000 { >> + compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; >> + reg = <0x0 0x23040000 0x0 0x10000>, >> + <0x0 0x23056000 0x0 0x100>; >> + reg-names = "stmmaceth", "rgmii"; > > Dumb question which should not stop this getting merged. > > Since this is now a MAC using a SERDES, do you still need the rmgii > registers? Can the silicon actually do RGMII? Indeed, the RGMII configuration area is necessary for managing clock settings, even when SERDES is utilized. For instance, the RGMII_CONFIG2_RGMII_CLK_SEL_CFG bit within RGMII_IO_MACRO_CONFIG2 is set in ethqos_configure_sgmii. > > Andrew -- Best Regards, Yijie