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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc76655absm333837566b.51.2026.02.17.03.50.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Feb 2026 03:50:06 -0800 (PST) Message-ID: <389dc762-bd20-44e5-a3fc-256b42f3c82a@oss.qualcomm.com> Date: Tue, 17 Feb 2026 12:50:03 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 13/13] i2c: qcom-geni: Enable I2C on SA8255p Qualcomm platforms To: Praveen Talari , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mukesh Kumar Savaliya , Viken Dadhaniya , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bjorn.andersson@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com Cc: prasad.sodagudi@oss.qualcomm.com, quic_vtanuku@quicinc.com, aniket.randive@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, jyothi.seerapu@oss.qualcomm.com, chiluka.harish@oss.qualcomm.com References: <20260206174112.4149893-1-praveen.talari@oss.qualcomm.com> <20260206174112.4149893-14-praveen.talari@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260206174112.4149893-14-praveen.talari@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 5uezERStJ2jxYave28UiZ3Aktr_Xnf3n X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE3MDA5OCBTYWx0ZWRfX6k+M1JyII69g +zr2jEaH4kVYoRYuSiDBS9i7Yxo+dVbNhQvw5d20AaOfhYx9vjCMo+Q9VqB2l70smPIAz2zoYbH y+lTFQ+Q3pjVVlpfh17eFDAj0S1VqlSvWO32gyxa5oKqGJGx0WryOrAvgmaWw3cVRyhq6W9HxB7 THkwHR8H5eoSnU1UDFn9LV7YX/2m+t2bd2Ok4GQXAchUIqlFirrfR9bdYIKl+J+rDAaKwStNSda KlrhEcxuKsx02LCaMN6TdTOqeIyDEUg5nPa/V8P7bjlq2g4AED33Zmyq8TyfCtB9zrjc0iM8r7a Wf1TXICw0CXJT5p/5HQLODKVdOBAizwS9JvdEhyKSFej05jz9T0yZ8zN2nGrnLNqIwfyqWx/kLE FBHxN/U4ar3AAIMx4eBJK0ioGTfAnTIKy13/6OYIYNB2VpjMTFruuWHBG3X0ob/lPZkRrYKlDSV v6naDgGRp0fEqJ9Kg7w== X-Authority-Analysis: v=2.4 cv=BpuQAIX5 c=1 sm=1 tr=0 ts=699455f0 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=uvtuXJDLjHB1kenEHasA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 5uezERStJ2jxYave28UiZ3Aktr_Xnf3n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170098 On 2/6/26 6:41 PM, Praveen Talari wrote: > The Qualcomm automotive SA8255p SoC relies on firmware to configure > platform resources, including clocks, interconnects and TLMM. > The driver requests resources operations over SCMI using power > and performance protocols. > > The SCMI power protocol enables or disables resources like clocks, > interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, > such as resume/suspend, to control power on/off. > > The SCMI performance protocol manages I2C frequency, with each > frequency rate represented by a performance level. The driver uses > geni_se_set_perf_opp() API to request the desired frequency rate.. > > As part of geni_se_set_perf_opp(), the OPP for the requested frequency > is obtained using dev_pm_opp_find_freq_floor() and the performance > level is set using dev_pm_opp_set_opp(). > > Acked-by: Viken Dadhaniya > Signed-off-by: Praveen Talari > --- [...] > @@ -215,6 +220,7 @@ static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) > val |= itr->t_low_cnt << LOW_COUNTER_SHFT; > val |= itr->t_cycle_cnt; > writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); > + return 0; ultra nit: a \n before return statements is preferred [...] > static const struct geni_i2c_desc i2c_master_hub = { > .no_dma_support = true, > .tx_fifo_depth = 16, > + .resources_init = geni_i2c_resources_init, > + .set_rate = qcom_geni_i2c_conf, > + .power_on = geni_se_resources_activate, > + .power_off = geni_se_resources_deactivate, > +}; > + > +static const struct geni_i2c_desc sa8255p_geni_i2c = { > + .resources_init = geni_se_domain_attach, > + .set_rate = geni_se_set_perf_opp, I noticed that because this lacks .power_on/off, the pinctrl_pm_select_xxx_state() functions are never called. Are the GPIOs managed through the power/perf domains of the QUP devices too? (I would assume not since there's a TLMM node in [0]) Konrad [0] https://lore.kernel.org/linux-arm-msm/20250422231249.871995-1-quic_djaggi@quicinc.com/