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Wed, 11 Dec 2024 20:30:34 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBKUXg8012320 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 20:30:33 GMT Received: from [10.216.57.155] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 12:30:27 -0800 Message-ID: <38f94094-c8ff-4c5a-aba5-6cc5acb81aa6@quicinc.com> Date: Thu, 12 Dec 2024 02:00:24 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes To: Konrad Dybcio , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , "Dmitry Baryshkov" , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" CC: , , , , , Jie Zhang References: <20241126-qcs615-gpu-dt-v1-0-a87782976dad@quicinc.com> <20241126-qcs615-gpu-dt-v1-2-a87782976dad@quicinc.com> <573d254c-9478-400a-9811-d8de7eba6dcb@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <573d254c-9478-400a-9811-d8de7eba6dcb@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pdNQlLHZDcohJTwOCTwOJWpFeFr-bAFy X-Proofpoint-GUID: pdNQlLHZDcohJTwOCTwOJWpFeFr-bAFy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=962 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110143 On 12/6/2024 1:16 AM, Konrad Dybcio wrote: > On 26.11.2024 3:06 PM, Akhil P Oommen wrote: >> From: Jie Zhang >> >> Add gpu and gmu nodes for qcs615 chipset. >> >> Signed-off-by: Jie Zhang >> Signed-off-by: Akhil P Oommen >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 86 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..f6a3fbbda962f01d6cf2d5c156ea1d1d846f310a 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -387,6 +387,11 @@ smem_region: smem@86000000 { >> no-map; >> hwlocks = <&tcsr_mutex 3>; >> }; >> + >> + pil_gpu_mem: pil-gpu@97715000 { >> + reg = <0x0 0x97715000 0x0 0x2000>; >> + no-map; >> + }; >> }; >> >> soc: soc@0 { >> @@ -508,6 +513,87 @@ qup_uart0_rx: qup-uart0-rx-state { >> }; >> }; >> >> + gpu: gpu@5000000 { >> + compatible = "qcom,adreno-612.0", "qcom,adreno"; >> + reg = <0x0 0x05000000 0x0 0x90000>; >> + reg-names = "kgsl_3d0_reg_memory"; >> + >> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, >> + <&gcc GCC_DDRSS_GPU_AXI_CLK>, >> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_CXO_CLK>, >> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > > This one belongs under the adreno_smmu node Yeah, right. Unlike downstream, smmu is a supplier of gpu here. -Akhil > > Konrad