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Thu, 12 Dec 2024 02:40:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IFnyVwDRBDMftoBMWsplpwELfuZa5WcAYks6wRIYQboTRQ2Ou+bmDhyPWtpyTxpRnJH5n6szw== X-Received: by 2002:a17:90b:53c6:b0:2ef:19d0:2261 with SMTP id 98e67ed59e1d1-2f127fbf2b1mr10723646a91.16.1734000037551; Thu, 12 Dec 2024 02:40:37 -0800 (PST) Received: from [10.92.207.127] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2f142daeee3sm936232a91.20.2024.12.12.02.40.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2024 02:40:37 -0800 (PST) Message-ID: <39012a4a-7d02-b954-bc06-53708b772a7c@oss.qualcomm.com> Date: Thu, 12 Dec 2024 16:10:30 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v2 0/4] PCI: dwc: Add support for configuring lane equalization presets Content-Language: en-US To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna chaitanya chundru References: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> From: Krishna Chaitanya Chundru In-Reply-To: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: pfHktwYq84pg-0xqV1T2i_0kPTHP1vZM X-Proofpoint-GUID: pfHktwYq84pg-0xqV1T2i_0kPTHP1vZM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 adultscore=0 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120075 Please ignore this series it has wrong patches I will send new series to fix this. - Krishna Chaitanya. On 12/12/2024 4:02 PM, Krishna Chaitanya Chundru wrote: > PCIe equalization presets are predefined settings used to optimize > signal integrity by compensating for signal loss and distortion in > high-speed data transmission. > > As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates > of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to > configure lane equalization presets for each lane to enhance the PCIe > link reliability. Each preset value represents a different combination > of pre-shoot and de-emphasis values. For each data rate, different > registers are defined: for 8.0 GT/s, registers are defined in section > 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has > an extra receiver preset hint, requiring 16 bits per lane, while the > remaining data rates use 8 bits per lane. > > Based on the number of lanes and the supported data rate, read the > device tree property and stores in the presets structure. > > Based upon the lane width and supported data rate update lane > equalization registers. > > This patch depends on the this dt binding pull request: https://github.com/devicetree-org/dt-schema/pull/146 > > Signed-off-by: Krishna Chaitanya Chundru > --- > Changes in v2: > - Fix the kernel test robot error > - As suggested by konrad use for loop and read "eq-presets-%ugts", (8 << i) > - Link to v1: https://lore.kernel.org/r/20241116-presets-v1-0-878a837a4fee@quicinc.com > > --- > Krishna chaitanya chundru (4): > arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties > PCI: of: Add API to retrieve equalization presets from device tree > PCI: dwc: Improve handling of PCIe lane configuration > PCI: dwc: Add support for new pci function op > > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++ > drivers/pci/controller/dwc/pcie-designware-host.c | 21 +++++++++++ > drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++- > drivers/pci/controller/dwc/pcie-designware.h | 1 + > drivers/pci/of.c | 45 +++++++++++++++++++++++ > drivers/pci/pci.h | 17 ++++++++- > 6 files changed, 103 insertions(+), 3 deletions(-) > --- > base-commit: 87d6aab2389e5ce0197d8257d5f8ee965a67c4cd > change-id: 20241212-preset_v2-549b7acda9b7 > > Best regards,