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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac23988cec9sm472280966b.144.2025.03.08.10.18.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 08 Mar 2025 10:18:46 -0800 (PST) Message-ID: <39389406-a581-46a7-bfa4-384d3bbd09fa@oss.qualcomm.com> Date: Sat, 8 Mar 2025 19:18:44 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq support To: Sricharan R , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20250127093128.2611247-1-quic_srichara@quicinc.com> <20250127093128.2611247-5-quic_srichara@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250127093128.2611247-5-quic_srichara@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: fpcB0DPqvaQSupwkD7LMmPbxcqtbWXk_ X-Authority-Analysis: v=2.4 cv=KK2gDEFo c=1 sm=1 tr=0 ts=67cc8a09 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=qTnuS0Aw-iaHhWJ6p_YA:9 a=QEXdDO2ut3YA:10 a=X5f3S4XyYk52BB0gviDM:22 a=uxP6HrT_eTzRwkO_Te1X:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: fpcB0DPqvaQSupwkD7LMmPbxcqtbWXk_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-08_07,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=920 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503080141 On 27.01.2025 10:31 AM, Sricharan R wrote: > From: Sricharan Ramabadhran subject: you're not enabling support, you're either enabling cpufreq (the feature), or adding support for it > Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for > CPU clock scaling. > > Signed-off-by: Sricharan Ramabadhran > --- [...] > + cpu_opp_table: opp-table-cpu { > + compatible = "operating-points-v2-kryo-cpu"; > + opp-shared; > + nvmem-cells = <&cpu_speed_bin>; > + > + /* > + * CPU supports two frequencies and the fuse has LValue instead > + * of limits. As only two frequencies are supported, considering > + * zero Lvalue as no limit and Lvalue as 1.4GHz limit. > + * ------------------------------------------------------------ > + * Frequency BIT1 BIT0 opp-supported-hw > + * 1.4GHz No Limit > + * ------------------------------------------------------------ > + * 1416000000 1 1 0x3 > + * 1800000000 0 1 0x1 > + * ------------------------------------------------------------ > + */ This is trivially inferred from the nodes below > + > + opp-1416000000 { > + opp-hz = /bits/ 64 <1416000000>; > + opp-microvolt = <1>; > + opp-supported-hw = <0x3>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1800000000 { > + opp-hz = /bits/ 64 <1800000000>; > + opp-microvolt = <2>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + }; > + > memory@80000000 { > device_type = "memory"; > /* We expect the bootloader to fill in the size */ > @@ -151,6 +202,18 @@ soc@0 { > #size-cells = <2>; > ranges = <0 0 0 0 0x10 0>; > > + qfprom@a6000 { > + compatible = "qcom,qfprom"; > + reg = <0x0 0xa6000 0x0 0x1000>; Please pad the address part to 8 hex digits with leading zeroes Konrad