Re: [PATCH 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller

[Sricharan Ramabadhran <quic_srichara@quicinc.com>]

On 1/28/2025 6:00 PM, Krzysztof Kozlowski wrote:
> On 28/01/2025 12:15, Sricharan Ramabadhran wrote:
>>
>>
>> On 1/28/2025 1:04 PM, Krzysztof Kozlowski wrote:
>>> On 27/01/2025 10:31, Sricharan R wrote:
>>>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>>>
>>>> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
>>>> The RCG and PLL have a separate register space from the GCC.
>>>> Also the L3 cache has a separate pll and needs to be scaled along
>>>> with the CPU.
>>>>
>>>> Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>>>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>>>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>>
>>> Considering that there were multiple conflicting patches coming from
>>> Qualcomm around IPQ SoCs and that we are in the merge window, I will
>>> skip this patch.
>>>
>>> I suspect this duplicates the other chip as well, but that's your task
>>> to sync up internally.
>>>
>> ok, but this .yaml is specific to IPQ5424 and would not conflict with
>> IPQ5332. That said, will post it after merge window as a part of
>> V3 (for other patch changes) to avoid any confusion.
> 
> 
> But maybe it is the same on ipq5332? or similar? Other works were
> totally de-synced and you ask community to sync them. That's not how it
> works.

This is different from ipq5332, hence we cannot re-use and would have
no conflicts as well.

Regards,
  Sricharan