From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B928D1E3799; Tue, 3 Dec 2024 08:04:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733213088; cv=none; b=esen2XRGlk1E5azn4eq+++Tb9isWq1rQaX5pmhiZI99KGs3RBIG2KV9KSUcGlYdhSR9Md/XPdfWCOmnDb5CuPAHkCK45v1ZSEtAdBnYyR0802OTOmP9YS/9B8Cu1AM0PEmBAjIATj09zQ0nOfBBxpy82j2lL9hS56KGebYi8UOw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733213088; c=relaxed/simple; bh=ogGT+tEgRtvtjmlcfLtQ/kpDFOq88/tpRAoBFCiwBaM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=itOwcQqse84E8j2h+MZeN7oVfwqdHLLq3otKe0gEOyc2jqnixopimkc0BiJORNNdRlPPjsdm+Na+A/8xi5whDPvw/ZbExV82CbAcGuQx/wmSCQZmdUXr4LeGBMJqP4ffVytYqScJJXMTqElsJWPpJpt+FhUtgW1UKs68Zgf7hJY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E1OLJTvP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E1OLJTvP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB014C4CECF; Tue, 3 Dec 2024 08:04:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733213088; bh=ogGT+tEgRtvtjmlcfLtQ/kpDFOq88/tpRAoBFCiwBaM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=E1OLJTvPW7aL/ytZ91En4Qv5s9bDlLu2RRY9dHv4QaFIhJzj0eNcqCmmSDx6b3Zq2 lk6GcRXGj/o8I857pOw9AWhVcjnuXxyELZvmPY9xwvtZvUdXA7jJcI/yCehkHMpMSv fvm1Oqp4YKbyiGtN7S3AB5kHwdFeYsCcjZTcghAfSVOJg5TOxLZnXlKTKmQ/mQNaQ1 kn82yo4q+CxS/xd8VXvgwRB1oyIsoBo2vHjQmjLG3ywMfC1E9Jw9BsXLprO1HVT+QE tHyPk8ye7D5aMmJZJIGD1CHbjTmRj3MG4efWlRsxufCSBDLxWVPMRUMEuPEbSy8suD 8FJ/4wV5L0aEA== Message-ID: <39f8e20a-e8c3-4625-abb1-9f35f416705d@kernel.org> Date: Tue, 3 Dec 2024 09:04:39 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] dt-bindings: display/msm: add stream 1 pixel clock binding To: Abhinav Kumar , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> <20241202-dp_mst_bindings-v1-3-9a9a43b0624a@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 03/12/2024 04:31, Abhinav Kumar wrote: > On some chipsets the display port controller can support more Which chipsets? > than one pixel stream (multi-stream transport). To support MST > on such chipsets, add the binding for stream 1 pixel clock for > display port controller. Since this mode is not supported on all > chipsets, add exception rules and min/max items to clearly mark > which chipsets support only SST mode (single stream) and which ones > support MST. > > Signed-off-by: Abhinav Kumar > --- > .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++++++ > .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- > 2 files changed, 38 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > index 9fe2bf0484d8..650d19e58277 100644 > --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml > @@ -50,30 +50,38 @@ properties: > maxItems: 1 > > clocks: > + minItems: 5 > items: > - description: AHB clock to enable register access > - description: Display Port AUX clock > - description: Display Port Link clock > - description: Link interface clock between DP and PHY > - description: Display Port stream 0 Pixel clock > + - description: Display Port stream 1 Pixel clock > > clock-names: > + minItems: 5 > items: > - const: core_iface > - const: core_aux > - const: ctrl_link > - const: ctrl_link_iface > - const: stream_pixel > + - const: stream_1_pixel > > assigned-clocks: > + minItems: 2 > items: > - description: link clock source > - description: stream 0 pixel clock source > + - description: stream 1 pixel clock source > > assigned-clock-parents: > + minItems: 2 > items: > - description: Link clock PLL output provided by PHY block > - description: Stream 0 pixel clock PLL output provided by PHY block > + - description: Stream 1 pixel clock PLL output provided by PHY block > > phys: > maxItems: 1 > @@ -175,6 +183,30 @@ allOf: > required: > - "#sound-dai-cells" > Missing if: narrowing this to 5 items for other devices. > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sa8775p-dp > + > + then: > + properties: > + clocks: Missing minItems, otherwise it is pointless. > + maxItems: 6 > + clock-names: > + items: > + - const: core_iface > + - const: core_aux > + - const: ctrl_link > + - const: ctrl_link_iface > + - const: stream_pixel > + - const: stream_1_pixel > + assigned-clocks: > + maxItems: 3 Missing minItems... or just drop, it's not accurate or not even correct. I can assign 4 clocks, why not? Or rather: why do you stop users from assigning 4 clocks? > + assigned-clock-parents: > + maxItems: 3 > + > additionalProperties: false Best regards, Krzysztof