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([2a01:e0a:982:cbb0:7f31:be49:5b98:50cd]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-422f9e2b306sm185956505e9.16.2024.06.18.05.17.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Jun 2024 05:17:24 -0700 (PDT) Message-ID: <3ad2d00f-6b5f-46c5-b95c-c8d68e8be736@linaro.org> Date: Tue, 18 Jun 2024 14:17:23 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH V4 8/8] arm64: dts: qcom: sm8650: Add video and camera clock controllers To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Satya Priya Kakitapalli , Ajit Pandey , Imran Shaik References: <20240602114439.1611-1-quic_jkona@quicinc.com> <20240602114439.1611-9-quic_jkona@quicinc.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 02/06/2024 13:44, Jagadeesh Kona wrote: > Add device nodes for video and camera clock controllers on Qualcomm > SM8650 platform. > > Signed-off-by: Jagadeesh Kona > Reviewed-by: Vladimir Zapolskiy > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 336c54242778..d964762b0532 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -4,10 +4,12 @@ > */ > > #include > +#include > #include > #include > #include > #include > +#include > #include > #include > #include > @@ -3315,6 +3317,30 @@ opp-202000000 { > }; > }; > > + videocc: clock-controller@aaf0000 { > + compatible = "qcom,sm8650-videocc"; > + reg = <0 0x0aaf0000 0 0x10000>; > + clocks = <&bi_tcxo_div2>, > + <&gcc GCC_VIDEO_AHB_CLK>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + camcc: clock-controller@ade0000 { > + compatible = "qcom,sm8650-camcc"; > + reg = <0 0x0ade0000 0 0x20000>; > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; If you resend, please respect the style of the SM8650 DT with blank lines to separate different properties groups: + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8650-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8650-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; And add the missing required-opps for the clock controllers like dispcc. Thanks, Neil > + > mdss: display-subsystem@ae00000 { > compatible = "qcom,sm8650-mdss"; > reg = <0 0x0ae00000 0 0x1000>;