* [PATCH v3 1/9] media: qcom: camss: Rename camss-csid-780.c to camss-csid-gen3.c
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 13:44 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 2/9] media: qcom: camss: Rename camss-vfe-780.c to camss-vfe-gen3.c Vikram Sharma
` (7 subsequent siblings)
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel
Rename the file camss-csid-780.c to camss-csid-gen3.c to enable
reuse of CSID logic across multiple SoCs.
The SA8775P SoC includes CSID 690, which is functionally very
similar to CSID 780, with only minor differences in register
bitfields. This rename prepares the codebase for supporting
additional SoCs without duplicating CSID logic.
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
drivers/media/platform/qcom/camss/Makefile | 2 +-
.../qcom/camss/{camss-csid-780.c => camss-csid-gen3.c} | 8 +++++---
.../qcom/camss/{camss-csid-780.h => camss-csid-gen3.h} | 9 +++++----
drivers/media/platform/qcom/camss/camss-csid.h | 2 +-
drivers/media/platform/qcom/camss/camss.c | 10 +++++-----
5 files changed, 17 insertions(+), 14 deletions(-)
rename drivers/media/platform/qcom/camss/{camss-csid-780.c => camss-csid-gen3.c} (98%)
rename drivers/media/platform/qcom/camss/{camss-csid-780.h => camss-csid-gen3.h} (84%)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index d26a9c24a430..ee869e69521a 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -8,7 +8,7 @@ qcom-camss-objs += \
camss-csid-4-7.o \
camss-csid-680.o \
camss-csid-gen2.o \
- camss-csid-780.o \
+ camss-csid-gen3.o \
camss-csiphy-2ph-1-0.o \
camss-csiphy-3ph-1-0.o \
camss-csiphy.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-780.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
similarity index 98%
rename from drivers/media/platform/qcom/camss/camss-csid-780.c
rename to drivers/media/platform/qcom/camss/camss-csid-gen3.c
index 4c720d177731..0941152ec301 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-780.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
@@ -4,6 +4,8 @@
*
* Copyright (c) 2024 Qualcomm Technologies, Inc.
*/
+
+
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
@@ -13,7 +15,7 @@
#include "camss.h"
#include "camss-csid.h"
-#include "camss-csid-780.h"
+#include "camss-csid-gen3.h"
#define CSID_IO_PATH_CFG0(csid) (0x4 * (csid))
#define OUTPUT_IFE_EN 0x100
@@ -259,7 +261,7 @@ static irqreturn_t csid_isr(int irq, void *dev)
if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) {
/*
- * For Titan 780, bus done and RUP IRQ have been moved to
+ * For Titan Gen3, bus done and RUP IRQ have been moved to
* CSID from VFE. Once CSID received bus done, need notify
* VFE of this event. Trigger VFE to handle bus done process.
*/
@@ -325,7 +327,7 @@ static void csid_subdev_init(struct csid_device *csid)
csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
}
-const struct csid_hw_ops csid_ops_780 = {
+const struct csid_hw_ops csid_ops_gen3 = {
.configure_stream = csid_configure_stream,
.configure_testgen_pattern = csid_configure_testgen_pattern,
.hw_version = csid_hw_version,
diff --git a/drivers/media/platform/qcom/camss/camss-csid-780.h b/drivers/media/platform/qcom/camss/camss-csid-gen3.h
similarity index 84%
rename from drivers/media/platform/qcom/camss/camss-csid-780.h
rename to drivers/media/platform/qcom/camss/camss-csid-gen3.h
index a990c66a60ff..e6298042ae74 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-780.h
+++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.h
@@ -1,13 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * camss-csid-780.h
+ * camss-csid-gen3.h
*
* Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module Generation 3
*
* Copyright (c) 2024 Qualcomm Technologies, Inc.
*/
-#ifndef __QC_MSM_CAMSS_CSID_780_H__
-#define __QC_MSM_CAMSS_CSID_780_H__
+#ifndef __QC_MSM_CAMSS_CSID_GEN3_H__
+#define __QC_MSM_CAMSS_CSID_GEN3_H__
#define DECODE_FORMAT_UNCOMPRESSED_8_BIT 0x1
#define DECODE_FORMAT_UNCOMPRESSED_10_BIT 0x2
@@ -18,8 +18,9 @@
#define DECODE_FORMAT_UNCOMPRESSED_24_BIT 0x7
#define DECODE_FORMAT_PAYLOAD_ONLY 0xf
+
#define PLAIN_FORMAT_PLAIN8 0x0 /* supports DPCM, UNCOMPRESSED_6/8_BIT */
#define PLAIN_FORMAT_PLAIN16 0x1 /* supports DPCM, UNCOMPRESSED_10/16_BIT */
#define PLAIN_FORMAT_PLAIN32 0x2 /* supports UNCOMPRESSED_20_BIT */
-#endif /* __QC_MSM_CAMSS_CSID_780_H__ */
+#endif /* __QC_MSM_CAMSS_CSID_GEN3_H__ */
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index 9dc826d8c8f6..62273ca9f199 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -215,7 +215,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
extern const struct csid_hw_ops csid_ops_680;
extern const struct csid_hw_ops csid_ops_gen2;
-extern const struct csid_hw_ops csid_ops_780;
+extern const struct csid_hw_ops csid_ops_gen3;
/*
* csid_is_lite - Check if CSID is CSID lite.
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 06f42875702f..1431e08dc04a 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2285,7 +2285,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
.csid = {
.is_lite = false,
.parent_dev_ops = &vfe_parent_dev_ops,
- .hw_ops = &csid_ops_780,
+ .hw_ops = &csid_ops_gen3,
.formats = &csid_formats_gen2
}
},
@@ -2300,7 +2300,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
.csid = {
.is_lite = false,
.parent_dev_ops = &vfe_parent_dev_ops,
- .hw_ops = &csid_ops_780,
+ .hw_ops = &csid_ops_gen3,
.formats = &csid_formats_gen2
}
},
@@ -2315,7 +2315,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
.csid = {
.is_lite = false,
.parent_dev_ops = &vfe_parent_dev_ops,
- .hw_ops = &csid_ops_780,
+ .hw_ops = &csid_ops_gen3,
.formats = &csid_formats_gen2
}
},
@@ -2330,7 +2330,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
.csid = {
.is_lite = true,
.parent_dev_ops = &vfe_parent_dev_ops,
- .hw_ops = &csid_ops_780,
+ .hw_ops = &csid_ops_gen3,
.formats = &csid_formats_gen2
}
},
@@ -2345,7 +2345,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
.csid = {
.is_lite = true,
.parent_dev_ops = &vfe_parent_dev_ops,
- .hw_ops = &csid_ops_780,
+ .hw_ops = &csid_ops_gen3,
.formats = &csid_formats_gen2
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 1/9] media: qcom: camss: Rename camss-csid-780.c to camss-csid-gen3.c
2025-07-03 17:19 ` [PATCH v3 1/9] media: qcom: camss: Rename camss-csid-780.c to camss-csid-gen3.c Vikram Sharma
@ 2025-07-28 13:44 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 13:44 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 03/07/2025 18:19, Vikram Sharma wrote:
> Rename the file camss-csid-780.c to camss-csid-gen3.c to enable
> reuse of CSID logic across multiple SoCs.
>
> The SA8775P SoC includes CSID 690, which is functionally very
> similar to CSID 780, with only minor differences in register
> bitfields. This rename prepares the codebase for supporting
> additional SoCs without duplicating CSID logic.
>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 2 +-
> .../qcom/camss/{camss-csid-780.c => camss-csid-gen3.c} | 8 +++++---
> .../qcom/camss/{camss-csid-780.h => camss-csid-gen3.h} | 9 +++++----
> drivers/media/platform/qcom/camss/camss-csid.h | 2 +-
> drivers/media/platform/qcom/camss/camss.c | 10 +++++-----
> 5 files changed, 17 insertions(+), 14 deletions(-)
> rename drivers/media/platform/qcom/camss/{camss-csid-780.c => camss-csid-gen3.c} (98%)
> rename drivers/media/platform/qcom/camss/{camss-csid-780.h => camss-csid-gen3.h} (84%)
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index d26a9c24a430..ee869e69521a 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -8,7 +8,7 @@ qcom-camss-objs += \
> camss-csid-4-7.o \
> camss-csid-680.o \
> camss-csid-gen2.o \
> - camss-csid-780.o \
> + camss-csid-gen3.o \
> camss-csiphy-2ph-1-0.o \
> camss-csiphy-3ph-1-0.o \
> camss-csiphy.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-780.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
> similarity index 98%
> rename from drivers/media/platform/qcom/camss/camss-csid-780.c
> rename to drivers/media/platform/qcom/camss/camss-csid-gen3.c
> index 4c720d177731..0941152ec301 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid-780.c
> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
> @@ -4,6 +4,8 @@
> *
> * Copyright (c) 2024 Qualcomm Technologies, Inc.
> */
> +
> +
Dead newlines.
> #include <linux/completion.h>
> #include <linux/delay.h>
> #include <linux/interrupt.h>
> @@ -13,7 +15,7 @@
>
> #include "camss.h"
> #include "camss-csid.h"
> -#include "camss-csid-780.h"
> +#include "camss-csid-gen3.h"
>
> #define CSID_IO_PATH_CFG0(csid) (0x4 * (csid))
> #define OUTPUT_IFE_EN 0x100
> @@ -259,7 +261,7 @@ static irqreturn_t csid_isr(int irq, void *dev)
>
> if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) {
> /*
> - * For Titan 780, bus done and RUP IRQ have been moved to
> + * For Titan Gen3, bus done and RUP IRQ have been moved to
> * CSID from VFE. Once CSID received bus done, need notify
> * VFE of this event. Trigger VFE to handle bus done process.
> */
> @@ -325,7 +327,7 @@ static void csid_subdev_init(struct csid_device *csid)
> csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
> }
>
> -const struct csid_hw_ops csid_ops_780 = {
> +const struct csid_hw_ops csid_ops_gen3 = {
> .configure_stream = csid_configure_stream,
> .configure_testgen_pattern = csid_configure_testgen_pattern,
> .hw_version = csid_hw_version,
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-780.h b/drivers/media/platform/qcom/camss/camss-csid-gen3.h
> similarity index 84%
> rename from drivers/media/platform/qcom/camss/camss-csid-780.h
> rename to drivers/media/platform/qcom/camss/camss-csid-gen3.h
> index a990c66a60ff..e6298042ae74 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid-780.h
> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.h
> @@ -1,13 +1,13 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * camss-csid-780.h
> + * camss-csid-gen3.h
> *
> * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module Generation 3
> *
> * Copyright (c) 2024 Qualcomm Technologies, Inc.
> */
> -#ifndef __QC_MSM_CAMSS_CSID_780_H__
> -#define __QC_MSM_CAMSS_CSID_780_H__
> +#ifndef __QC_MSM_CAMSS_CSID_GEN3_H__
> +#define __QC_MSM_CAMSS_CSID_GEN3_H__
>
> #define DECODE_FORMAT_UNCOMPRESSED_8_BIT 0x1
> #define DECODE_FORMAT_UNCOMPRESSED_10_BIT 0x2
> @@ -18,8 +18,9 @@
> #define DECODE_FORMAT_UNCOMPRESSED_24_BIT 0x7
> #define DECODE_FORMAT_PAYLOAD_ONLY 0xf
>
> +
another dead newline
> #define PLAIN_FORMAT_PLAIN8 0x0 /* supports DPCM, UNCOMPRESSED_6/8_BIT */
> #define PLAIN_FORMAT_PLAIN16 0x1 /* supports DPCM, UNCOMPRESSED_10/16_BIT */
> #define PLAIN_FORMAT_PLAIN32 0x2 /* supports UNCOMPRESSED_20_BIT */
>
> -#endif /* __QC_MSM_CAMSS_CSID_780_H__ */
> +#endif /* __QC_MSM_CAMSS_CSID_GEN3_H__ */
> diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
> index 9dc826d8c8f6..62273ca9f199 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid.h
> +++ b/drivers/media/platform/qcom/camss/camss-csid.h
> @@ -215,7 +215,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
> extern const struct csid_hw_ops csid_ops_4_7;
> extern const struct csid_hw_ops csid_ops_680;
> extern const struct csid_hw_ops csid_ops_gen2;
> -extern const struct csid_hw_ops csid_ops_780;
> +extern const struct csid_hw_ops csid_ops_gen3;
>
> /*
> * csid_is_lite - Check if CSID is CSID lite.
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 06f42875702f..1431e08dc04a 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2285,7 +2285,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
> .csid = {
> .is_lite = false,
> .parent_dev_ops = &vfe_parent_dev_ops,
> - .hw_ops = &csid_ops_780,
> + .hw_ops = &csid_ops_gen3,
> .formats = &csid_formats_gen2
> }
> },
> @@ -2300,7 +2300,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
> .csid = {
> .is_lite = false,
> .parent_dev_ops = &vfe_parent_dev_ops,
> - .hw_ops = &csid_ops_780,
> + .hw_ops = &csid_ops_gen3,
> .formats = &csid_formats_gen2
> }
> },
> @@ -2315,7 +2315,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
> .csid = {
> .is_lite = false,
> .parent_dev_ops = &vfe_parent_dev_ops,
> - .hw_ops = &csid_ops_780,
> + .hw_ops = &csid_ops_gen3,
> .formats = &csid_formats_gen2
> }
> },
> @@ -2330,7 +2330,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
> .csid = {
> .is_lite = true,
> .parent_dev_ops = &vfe_parent_dev_ops,
> - .hw_ops = &csid_ops_780,
> + .hw_ops = &csid_ops_gen3,
> .formats = &csid_formats_gen2
> }
> },
> @@ -2345,7 +2345,7 @@ static const struct camss_subdev_resources csid_res_8550[] = {
> .csid = {
> .is_lite = true,
> .parent_dev_ops = &vfe_parent_dev_ops,
> - .hw_ops = &csid_ops_780,
> + .hw_ops = &csid_ops_gen3,
> .formats = &csid_formats_gen2
> }
> }
I can fix those newlines, no need for a v4.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 2/9] media: qcom: camss: Rename camss-vfe-780.c to camss-vfe-gen3.c
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
2025-07-03 17:19 ` [PATCH v3 1/9] media: qcom: camss: Rename camss-csid-780.c to camss-csid-gen3.c Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 13:45 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 3/9] media: dt-bindings: Add qcom,sa8775p-camss compatible Vikram Sharma
` (6 subsequent siblings)
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel
Rename the file camss-vfe-780.c to camss-vfe-gen3.c to enable
reuse of VFE logic across multiple SoCs.
The SA8775P SoC includes VFE 690, which is very similar to
VFE 780, with only minor differences in register bitfields.
Rename prepares the codebase for supporting additional SoCs
without duplicating VFE logic.
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
drivers/media/platform/qcom/camss/Makefile | 2 +-
.../qcom/camss/{camss-vfe-780.c => camss-vfe-gen3.c} | 8 ++++----
drivers/media/platform/qcom/camss/camss-vfe.h | 2 +-
drivers/media/platform/qcom/camss/camss.c | 10 +++++-----
4 files changed, 11 insertions(+), 11 deletions(-)
rename drivers/media/platform/qcom/camss/{camss-vfe-780.c => camss-vfe-gen3.c} (96%)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index ee869e69521a..76845a456c45 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -19,7 +19,7 @@ qcom-camss-objs += \
camss-vfe-17x.o \
camss-vfe-480.o \
camss-vfe-680.o \
- camss-vfe-780.o \
+ camss-vfe-gen3.o \
camss-vfe-gen1.o \
camss-vfe.o \
camss-video.o \
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-780.c b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
similarity index 96%
rename from drivers/media/platform/qcom/camss/camss-vfe-780.c
rename to drivers/media/platform/qcom/camss/camss-vfe-gen3.c
index b9812d70f91b..93d16b0951e9 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-780.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550)
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen3
*
* Copyright (c) 2024 Qualcomm Technologies, Inc.
*/
@@ -113,14 +113,14 @@ static inline void vfe_reg_update_clear(struct vfe_device *vfe,
camss_reg_update(vfe->camss, vfe->id, port_id, true);
}
-static const struct camss_video_ops vfe_video_ops_780 = {
+static const struct camss_video_ops vfe_video_ops_gen3 = {
.queue_buffer = vfe_queue_buffer_v2,
.flush_buffers = vfe_flush_buffers,
};
static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
{
- vfe->video_ops = vfe_video_ops_780;
+ vfe->video_ops = vfe_video_ops_gen3;
}
static void vfe_global_reset(struct vfe_device *vfe)
@@ -140,7 +140,7 @@ static int vfe_halt(struct vfe_device *vfe)
return 0;
}
-const struct vfe_hw_ops vfe_ops_780 = {
+const struct vfe_hw_ops vfe_ops_gen3 = {
.global_reset = vfe_global_reset,
.hw_version = vfe_hw_version,
.isr = vfe_isr,
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index a23f666be753..02d9162ffd93 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -244,7 +244,7 @@ extern const struct vfe_hw_ops vfe_ops_4_8;
extern const struct vfe_hw_ops vfe_ops_170;
extern const struct vfe_hw_ops vfe_ops_480;
extern const struct vfe_hw_ops vfe_ops_680;
-extern const struct vfe_hw_ops vfe_ops_780;
+extern const struct vfe_hw_ops vfe_ops_gen3;
int vfe_get(struct vfe_device *vfe);
void vfe_put(struct vfe_device *vfe);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 1431e08dc04a..310b5cd8de5f 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2371,7 +2371,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
.is_lite = false,
.has_pd = true,
.pd_name = "ife0",
- .hw_ops = &vfe_ops_780,
+ .hw_ops = &vfe_ops_gen3,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -2395,7 +2395,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
.is_lite = false,
.has_pd = true,
.pd_name = "ife1",
- .hw_ops = &vfe_ops_780,
+ .hw_ops = &vfe_ops_gen3,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -2419,7 +2419,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
.is_lite = false,
.has_pd = true,
.pd_name = "ife2",
- .hw_ops = &vfe_ops_780,
+ .hw_ops = &vfe_ops_gen3,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -2441,7 +2441,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
.vfe = {
.line_num = 4,
.is_lite = true,
- .hw_ops = &vfe_ops_780,
+ .hw_ops = &vfe_ops_gen3,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -2463,7 +2463,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
.vfe = {
.line_num = 4,
.is_lite = true,
- .hw_ops = &vfe_ops_780,
+ .hw_ops = &vfe_ops_gen3,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 2/9] media: qcom: camss: Rename camss-vfe-780.c to camss-vfe-gen3.c
2025-07-03 17:19 ` [PATCH v3 2/9] media: qcom: camss: Rename camss-vfe-780.c to camss-vfe-gen3.c Vikram Sharma
@ 2025-07-28 13:45 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 13:45 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 03/07/2025 18:19, Vikram Sharma wrote:
> Rename the file camss-vfe-780.c to camss-vfe-gen3.c to enable
> reuse of VFE logic across multiple SoCs.
>
> The SA8775P SoC includes VFE 690, which is very similar to
> VFE 780, with only minor differences in register bitfields.
> Rename prepares the codebase for supporting additional SoCs
> without duplicating VFE logic.
>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 2 +-
> .../qcom/camss/{camss-vfe-780.c => camss-vfe-gen3.c} | 8 ++++----
> drivers/media/platform/qcom/camss/camss-vfe.h | 2 +-
> drivers/media/platform/qcom/camss/camss.c | 10 +++++-----
> 4 files changed, 11 insertions(+), 11 deletions(-)
> rename drivers/media/platform/qcom/camss/{camss-vfe-780.c => camss-vfe-gen3.c} (96%)
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index ee869e69521a..76845a456c45 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -19,7 +19,7 @@ qcom-camss-objs += \
> camss-vfe-17x.o \
> camss-vfe-480.o \
> camss-vfe-680.o \
> - camss-vfe-780.o \
> + camss-vfe-gen3.o \
> camss-vfe-gen1.o \
> camss-vfe.o \
> camss-video.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-780.c b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
> similarity index 96%
> rename from drivers/media/platform/qcom/camss/camss-vfe-780.c
> rename to drivers/media/platform/qcom/camss/camss-vfe-gen3.c
> index b9812d70f91b..93d16b0951e9 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe-780.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550)
> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen3
> *
> * Copyright (c) 2024 Qualcomm Technologies, Inc.
> */
> @@ -113,14 +113,14 @@ static inline void vfe_reg_update_clear(struct vfe_device *vfe,
> camss_reg_update(vfe->camss, vfe->id, port_id, true);
> }
>
> -static const struct camss_video_ops vfe_video_ops_780 = {
> +static const struct camss_video_ops vfe_video_ops_gen3 = {
> .queue_buffer = vfe_queue_buffer_v2,
> .flush_buffers = vfe_flush_buffers,
> };
>
> static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
> {
> - vfe->video_ops = vfe_video_ops_780;
> + vfe->video_ops = vfe_video_ops_gen3;
> }
>
> static void vfe_global_reset(struct vfe_device *vfe)
> @@ -140,7 +140,7 @@ static int vfe_halt(struct vfe_device *vfe)
> return 0;
> }
>
> -const struct vfe_hw_ops vfe_ops_780 = {
> +const struct vfe_hw_ops vfe_ops_gen3 = {
> .global_reset = vfe_global_reset,
> .hw_version = vfe_hw_version,
> .isr = vfe_isr,
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
> index a23f666be753..02d9162ffd93 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.h
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h
> @@ -244,7 +244,7 @@ extern const struct vfe_hw_ops vfe_ops_4_8;
> extern const struct vfe_hw_ops vfe_ops_170;
> extern const struct vfe_hw_ops vfe_ops_480;
> extern const struct vfe_hw_ops vfe_ops_680;
> -extern const struct vfe_hw_ops vfe_ops_780;
> +extern const struct vfe_hw_ops vfe_ops_gen3;
>
> int vfe_get(struct vfe_device *vfe);
> void vfe_put(struct vfe_device *vfe);
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 1431e08dc04a..310b5cd8de5f 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2371,7 +2371,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
> .is_lite = false,
> .has_pd = true,
> .pd_name = "ife0",
> - .hw_ops = &vfe_ops_780,
> + .hw_ops = &vfe_ops_gen3,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -2395,7 +2395,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
> .is_lite = false,
> .has_pd = true,
> .pd_name = "ife1",
> - .hw_ops = &vfe_ops_780,
> + .hw_ops = &vfe_ops_gen3,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -2419,7 +2419,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
> .is_lite = false,
> .has_pd = true,
> .pd_name = "ife2",
> - .hw_ops = &vfe_ops_780,
> + .hw_ops = &vfe_ops_gen3,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -2441,7 +2441,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
> .vfe = {
> .line_num = 4,
> .is_lite = true,
> - .hw_ops = &vfe_ops_780,
> + .hw_ops = &vfe_ops_gen3,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -2463,7 +2463,7 @@ static const struct camss_subdev_resources vfe_res_8550[] = {
> .vfe = {
> .line_num = 4,
> .is_lite = true,
> - .hw_ops = &vfe_ops_780,
> + .hw_ops = &vfe_ops_gen3,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 3/9] media: dt-bindings: Add qcom,sa8775p-camss compatible
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
2025-07-03 17:19 ` [PATCH v3 1/9] media: qcom: camss: Rename camss-csid-780.c to camss-csid-gen3.c Vikram Sharma
2025-07-03 17:19 ` [PATCH v3 2/9] media: qcom: camss: Rename camss-vfe-780.c to camss-vfe-gen3.c Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 13:47 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 4/9] arm64: dts: qcom: sa8775p: Add support for camss Vikram Sharma
` (5 subsequent siblings)
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel, Wenmeng Liu,
Krzysztof Kozlowski
Add the compatible string "qcom,sa8775p-camss" to support the
Camera Subsystem (CAMSS) on the Qualcomm SA8775P platform.
The SA8775P platform provides:
- 2 x VFE (version 690), each with 3 RDI
- 5 x VFE Lite (version 690), each with 6 RDI
- 2 x CSID (version 690)
- 5 x CSID Lite (version 690)
- 4 x CSIPHY (version 690)
- 3 x TPG
SA8775P is the first Qualcomm SoC to introduce a CSIPHY-based
Test Pattern Generator (TPG).
Co-developed-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/media/qcom,sa8775p-camss.yaml | 361 ++++++++++++++++++
1 file changed, 361 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
new file mode 100644
index 000000000000..b9f351546cd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
@@ -0,0 +1,361 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sa8775p-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SA8775P CAMSS ISP
+
+maintainers:
+ - Vikram Sharma <quic_vikramsa@quicinc.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sa8775p-camss
+
+ reg:
+ maxItems: 22
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csid_lite2
+ - const: csid_lite3
+ - const: csid_lite4
+ - const: csid_wrapper
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe_lite2
+ - const: vfe_lite3
+ - const: vfe_lite4
+
+ clocks:
+ maxItems: 28
+
+ clock-names:
+ items:
+ - const: camnoc_axi
+ - const: core_ahb
+ - const: cpas_ahb
+ - const: cpas_fast_ahb_clk
+ - const: cpas_vfe_lite
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: csid
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy_rx
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: icp_ahb
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 21
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csid_lite2
+ - const: csid_lite3
+ - const: csid_lite4
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe_lite2
+ - const: vfe_lite3
+ - const: vfe_lite4
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_0
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: top
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-3]+$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input port for receiving CSI data on CSIPHY 0-3.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+ #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+ #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ac7a000 {
+ compatible = "qcom,sa8775p-camss";
+
+ reg = <0x0 0xac7a000 0x0 0x0f00>,
+ <0x0 0xac7c000 0x0 0x0f00>,
+ <0x0 0xac84000 0x0 0x0f00>,
+ <0x0 0xac88000 0x0 0x0f00>,
+ <0x0 0xac8c000 0x0 0x0f00>,
+ <0x0 0xac90000 0x0 0x0f00>,
+ <0x0 0xac94000 0x0 0x0f00>,
+ <0x0 0xac78000 0x0 0x1000>,
+ <0x0 0xac9c000 0x0 0x2000>,
+ <0x0 0xac9e000 0x0 0x2000>,
+ <0x0 0xaca0000 0x0 0x2000>,
+ <0x0 0xaca2000 0x0 0x2000>,
+ <0x0 0xacac000 0x0 0x0400>,
+ <0x0 0xacad000 0x0 0x0400>,
+ <0x0 0xacae000 0x0 0x0400>,
+ <0x0 0xac4d000 0x0 0xd000>,
+ <0x0 0xac5a000 0x0 0xd000>,
+ <0x0 0xac85000 0x0 0x0d00>,
+ <0x0 0xac89000 0x0 0x0d00>,
+ <0x0 0xac8d000 0x0 0x0d00>,
+ <0x0 0xac91000 0x0 0x0d00>,
+ <0x0 0xac95000 0x0 0x0d00>;
+ reg-names = "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csid_wrapper",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb_clk",
+ "cpas_vfe_lite",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0";
+
+ iommus = <&apps_smmu 0x3400 0x20>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "top";
+
+ vdda-phy-supply = <&vreg_l4a_0p88>;
+ vdda-pll-supply = <&vreg_l1c_1p2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 3/9] media: dt-bindings: Add qcom,sa8775p-camss compatible
2025-07-03 17:19 ` [PATCH v3 3/9] media: dt-bindings: Add qcom,sa8775p-camss compatible Vikram Sharma
@ 2025-07-28 13:47 ` Bryan O'Donoghue
2025-07-30 9:14 ` Vikram Sharma
0 siblings, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 13:47 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel, Wenmeng Liu, Krzysztof Kozlowski
On 03/07/2025 18:19, Vikram Sharma wrote:
> Add the compatible string "qcom,sa8775p-camss" to support the
> Camera Subsystem (CAMSS) on the Qualcomm SA8775P platform.
>
> The SA8775P platform provides:
> - 2 x VFE (version 690), each with 3 RDI
> - 5 x VFE Lite (version 690), each with 6 RDI
> - 2 x CSID (version 690)
> - 5 x CSID Lite (version 690)
> - 4 x CSIPHY (version 690)
> - 3 x TPG
>
> SA8775P is the first Qualcomm SoC to introduce a CSIPHY-based
> Test Pattern Generator (TPG).
>
> Co-developed-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
> Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/media/qcom,sa8775p-camss.yaml | 361 ++++++++++++++++++
> 1 file changed, 361 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
> new file mode 100644
> index 000000000000..b9f351546cd1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
> @@ -0,0 +1,361 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sa8775p-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SA8775P CAMSS ISP
> +
> +maintainers:
> + - Vikram Sharma <quic_vikramsa@quicinc.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,sa8775p-camss
> +
> + reg:
> + maxItems: 22
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_lite2
> + - const: csid_lite3
> + - const: csid_lite4
> + - const: csid_wrapper
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: vfe_lite2
> + - const: vfe_lite3
> + - const: vfe_lite4
> +
> + clocks:
> + maxItems: 28
> +
> + clock-names:
> + items:
> + - const: camnoc_axi
> + - const: core_ahb
> + - const: cpas_ahb
> + - const: cpas_fast_ahb_clk
> + - const: cpas_vfe_lite
> + - const: cpas_vfe0
> + - const: cpas_vfe1
> + - const: csid
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy_rx
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> + - const: icp_ahb
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 21
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csid_lite2
> + - const: csid_lite3
> + - const: csid_lite4
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: vfe_lite2
> + - const: vfe_lite3
> + - const: vfe_lite4
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_0
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + items:
> + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
> +
> + power-domain-names:
> + items:
> + - const: top
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-3]+$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input port for receiving CSI data on CSIPHY 0-3.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp@ac7a000 {
> + compatible = "qcom,sa8775p-camss";
> +
> + reg = <0x0 0xac7a000 0x0 0x0f00>,
> + <0x0 0xac7c000 0x0 0x0f00>,
> + <0x0 0xac84000 0x0 0x0f00>,
> + <0x0 0xac88000 0x0 0x0f00>,
> + <0x0 0xac8c000 0x0 0x0f00>,
> + <0x0 0xac90000 0x0 0x0f00>,
> + <0x0 0xac94000 0x0 0x0f00>,
> + <0x0 0xac78000 0x0 0x1000>,
> + <0x0 0xac9c000 0x0 0x2000>,
> + <0x0 0xac9e000 0x0 0x2000>,
> + <0x0 0xaca0000 0x0 0x2000>,
> + <0x0 0xaca2000 0x0 0x2000>,
> + <0x0 0xacac000 0x0 0x0400>,
> + <0x0 0xacad000 0x0 0x0400>,
> + <0x0 0xacae000 0x0 0x0400>,
> + <0x0 0xac4d000 0x0 0xd000>,
> + <0x0 0xac5a000 0x0 0xd000>,
> + <0x0 0xac85000 0x0 0x0d00>,
> + <0x0 0xac89000 0x0 0x0d00>,
> + <0x0 0xac8d000 0x0 0x0d00>,
> + <0x0 0xac91000 0x0 0x0d00>,
> + <0x0 0xac95000 0x0 0x0d00>;
> + reg-names = "csid0",
> + "csid1",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_lite2",
> + "csid_lite3",
> + "csid_lite4",
> + "csid_wrapper",
csid_wrapper is IMO the "main" register bank and as such should come
first in the list of registers.
Please update this description to reflect, remembering to amend your
isp@address here and in your dts.
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "tpg0",
> + "tpg1",
> + "tpg2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite0",
> + "vfe_lite1",
> + "vfe_lite2",
> + "vfe_lite3",
> + "vfe_lite4";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CORE_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
> + <&camcc CAM_CC_CPAS_IFE_1_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAM_CC_ICP_AHB_CLK>,
> + <&camcc CAM_CC_IFE_0_CLK>,
> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_1_CLK>,
> + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
> + clock-names = "camnoc_axi",
> + "core_ahb",
> + "cpas_ahb",
> + "cpas_fast_ahb_clk",
> + "cpas_vfe_lite",
> + "cpas_vfe0",
> + "cpas_vfe1",
> + "csid",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy_rx",
> + "gcc_axi_hf",
> + "gcc_axi_sf",
> + "icp_ahb",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid";
> +
> + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_lite2",
> + "csid_lite3",
> + "csid_lite4",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "tpg0",
> + "tpg1",
> + "tpg2",
> + "vfe0",
> + "vfe1",
> + "vfe_lite0",
> + "vfe_lite1",
> + "vfe_lite2",
> + "vfe_lite3",
> + "vfe_lite4";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_0";
> +
> + iommus = <&apps_smmu 0x3400 0x20>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + power-domain-names = "top";
> +
> + vdda-phy-supply = <&vreg_l4a_0p88>;
> + vdda-pll-supply = <&vreg_l1c_1p2>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
Otherwise that this looks fine, please fix and then add.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 3/9] media: dt-bindings: Add qcom,sa8775p-camss compatible
2025-07-28 13:47 ` Bryan O'Donoghue
@ 2025-07-30 9:14 ` Vikram Sharma
0 siblings, 0 replies; 22+ messages in thread
From: Vikram Sharma @ 2025-07-30 9:14 UTC (permalink / raw)
To: Bryan O'Donoghue, rfoss, todor.too, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel, Wenmeng Liu, Krzysztof Kozlowski
On 7/28/2025 7:17 PM, Bryan O'Donoghue wrote:
> WARNING: This email originated from outside of Qualcomm. Please be
> wary of any links or attachments, and do not enable macros.
>
> On 03/07/2025 18:19, Vikram Sharma wrote:
>> Add the compatible string "qcom,sa8775p-camss" to support the
>> Camera Subsystem (CAMSS) on the Qualcomm SA8775P platform.
>>
>> The SA8775P platform provides:
>> - 2 x VFE (version 690), each with 3 RDI
>> - 5 x VFE Lite (version 690), each with 6 RDI
>> - 2 x CSID (version 690)
>> - 5 x CSID Lite (version 690)
>> - 4 x CSIPHY (version 690)
>> - 3 x TPG
>>
>> SA8775P is the first Qualcomm SoC to introduce a CSIPHY-based
>> Test Pattern Generator (TPG).
>>
>> Co-developed-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
>> Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
>> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>> .../bindings/media/qcom,sa8775p-camss.yaml | 361 ++++++++++++++++++
>> 1 file changed, 361 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
>> b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
>> new file mode 100644
>> index 000000000000..b9f351546cd1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml
>> @@ -0,0 +1,361 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,sa8775p-camss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SA8775P CAMSS ISP
>> +
>> +maintainers:
>> + - Vikram Sharma <quic_vikramsa@quicinc.com>
>> +
>> +description:
>> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sa8775p-camss
>> +
>> + reg:
>> + maxItems: 22
>> +
>> + reg-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid_lite0
>> + - const: csid_lite1
>> + - const: csid_lite2
>> + - const: csid_lite3
>> + - const: csid_lite4
>> + - const: csid_wrapper
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: csiphy3
>> + - const: tpg0
>> + - const: tpg1
>> + - const: tpg2
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe_lite0
>> + - const: vfe_lite1
>> + - const: vfe_lite2
>> + - const: vfe_lite3
>> + - const: vfe_lite4
>> +
>> + clocks:
>> + maxItems: 28
>> +
>> + clock-names:
>> + items:
>> + - const: camnoc_axi
>> + - const: core_ahb
>> + - const: cpas_ahb
>> + - const: cpas_fast_ahb_clk
>> + - const: cpas_vfe_lite
>> + - const: cpas_vfe0
>> + - const: cpas_vfe1
>> + - const: csid
>> + - const: csiphy0
>> + - const: csiphy0_timer
>> + - const: csiphy1
>> + - const: csiphy1_timer
>> + - const: csiphy2
>> + - const: csiphy2_timer
>> + - const: csiphy3
>> + - const: csiphy3_timer
>> + - const: csiphy_rx
>> + - const: gcc_axi_hf
>> + - const: gcc_axi_sf
>> + - const: icp_ahb
>> + - const: vfe0
>> + - const: vfe0_fast_ahb
>> + - const: vfe1
>> + - const: vfe1_fast_ahb
>> + - const: vfe_lite
>> + - const: vfe_lite_ahb
>> + - const: vfe_lite_cphy_rx
>> + - const: vfe_lite_csid
>> +
>> + interrupts:
>> + maxItems: 21
>> +
>> + interrupt-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid_lite0
>> + - const: csid_lite1
>> + - const: csid_lite2
>> + - const: csid_lite3
>> + - const: csid_lite4
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: csiphy3
>> + - const: tpg0
>> + - const: tpg1
>> + - const: tpg2
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe_lite0
>> + - const: vfe_lite1
>> + - const: vfe_lite2
>> + - const: vfe_lite3
>> + - const: vfe_lite4
>> +
>> + interconnects:
>> + maxItems: 2
>> +
>> + interconnect-names:
>> + items:
>> + - const: ahb
>> + - const: hf_0
>> +
>> + iommus:
>> + maxItems: 1
>> +
>> + power-domains:
>> + items:
>> + - description: Titan GDSC - Titan ISP Block, Global
>> Distributed Switch Controller.
>> +
>> + power-domain-names:
>> + items:
>> + - const: top
>> +
>> + vdda-phy-supply:
>> + description:
>> + Phandle to a regulator supply to PHY core block.
>> +
>> + vdda-pll-supply:
>> + description:
>> + Phandle to 1.8V regulator supply to PHY refclk pll block.
>> +
>> + ports:
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + description:
>> + CSI input ports.
>> +
>> + patternProperties:
>> + "^port@[0-3]+$":
>> + $ref: /schemas/graph.yaml#/$defs/port-base
>> + unevaluatedProperties: false
>> + description:
>> + Input port for receiving CSI data on CSIPHY 0-3.
>> +
>> + properties:
>> + endpoint:
>> + $ref: video-interfaces.yaml#
>> + unevaluatedProperties: false
>> +
>> + properties:
>> + data-lanes:
>> + minItems: 1
>> + maxItems: 4
>> +
>> + required:
>> + - data-lanes
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - clocks
>> + - clock-names
>> + - interrupts
>> + - interrupt-names
>> + - interconnects
>> + - interconnect-names
>> + - iommus
>> + - power-domains
>> + - power-domain-names
>> + - vdda-phy-supply
>> + - vdda-pll-supply
>> + - ports
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
>> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
>> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
>> + #include <dt-bindings/interconnect/qcom,icc.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + isp@ac7a000 {
>> + compatible = "qcom,sa8775p-camss";
>> +
>> + reg = <0x0 0xac7a000 0x0 0x0f00>,
>> + <0x0 0xac7c000 0x0 0x0f00>,
>> + <0x0 0xac84000 0x0 0x0f00>,
>> + <0x0 0xac88000 0x0 0x0f00>,
>> + <0x0 0xac8c000 0x0 0x0f00>,
>> + <0x0 0xac90000 0x0 0x0f00>,
>> + <0x0 0xac94000 0x0 0x0f00>,
>> + <0x0 0xac78000 0x0 0x1000>,
>> + <0x0 0xac9c000 0x0 0x2000>,
>> + <0x0 0xac9e000 0x0 0x2000>,
>> + <0x0 0xaca0000 0x0 0x2000>,
>> + <0x0 0xaca2000 0x0 0x2000>,
>> + <0x0 0xacac000 0x0 0x0400>,
>> + <0x0 0xacad000 0x0 0x0400>,
>> + <0x0 0xacae000 0x0 0x0400>,
>> + <0x0 0xac4d000 0x0 0xd000>,
>> + <0x0 0xac5a000 0x0 0xd000>,
>> + <0x0 0xac85000 0x0 0x0d00>,
>> + <0x0 0xac89000 0x0 0x0d00>,
>> + <0x0 0xac8d000 0x0 0x0d00>,
>> + <0x0 0xac91000 0x0 0x0d00>,
>> + <0x0 0xac95000 0x0 0x0d00>;
>> + reg-names = "csid0",
>> + "csid1",
>> + "csid_lite0",
>> + "csid_lite1",
>> + "csid_lite2",
>> + "csid_lite3",
>> + "csid_lite4",
>> + "csid_wrapper",
>
> csid_wrapper is IMO the "main" register bank and as such should come
> first in the list of registers.
>
> Please update this description to reflect, remembering to amend your
> isp@address here and in your dts.
Thanks for your comment Bryan.
As per our earlier discussion we agreed to keep it as per 8550. Please
confirm if we need to change that?
https://lore.kernel.org/all/b1ea0500-595f-48d6-9358-649c25fd4ee9@linaro.org/#t
>
>> + "csiphy0",
>> + "csiphy1",
>> + "csiphy2",
>> + "csiphy3",
>> + "tpg0",
>> + "tpg1",
>> + "tpg2",
>> + "vfe0",
>> + "vfe1",
>> + "vfe_lite0",
>> + "vfe_lite1",
>> + "vfe_lite2",
>> + "vfe_lite3",
>> + "vfe_lite4";
>> +
>> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
>> + <&camcc CAM_CC_CORE_AHB_CLK>,
>> + <&camcc CAM_CC_CPAS_AHB_CLK>,
>> + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
>> + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
>> + <&camcc CAM_CC_CPAS_IFE_0_CLK>,
>> + <&camcc CAM_CC_CPAS_IFE_1_CLK>,
>> + <&camcc CAM_CC_CSID_CLK>,
>> + <&camcc CAM_CC_CSIPHY0_CLK>,
>> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
>> + <&camcc CAM_CC_CSIPHY1_CLK>,
>> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
>> + <&camcc CAM_CC_CSIPHY2_CLK>,
>> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
>> + <&camcc CAM_CC_CSIPHY3_CLK>,
>> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
>> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
>> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
>> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
>> + <&camcc CAM_CC_ICP_AHB_CLK>,
>> + <&camcc CAM_CC_IFE_0_CLK>,
>> + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
>> + <&camcc CAM_CC_IFE_1_CLK>,
>> + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
>> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
>> + clock-names = "camnoc_axi",
>> + "core_ahb",
>> + "cpas_ahb",
>> + "cpas_fast_ahb_clk",
>> + "cpas_vfe_lite",
>> + "cpas_vfe0",
>> + "cpas_vfe1",
>> + "csid",
>> + "csiphy0",
>> + "csiphy0_timer",
>> + "csiphy1",
>> + "csiphy1_timer",
>> + "csiphy2",
>> + "csiphy2_timer",
>> + "csiphy3",
>> + "csiphy3_timer",
>> + "csiphy_rx",
>> + "gcc_axi_hf",
>> + "gcc_axi_sf",
>> + "icp_ahb",
>> + "vfe0",
>> + "vfe0_fast_ahb",
>> + "vfe1",
>> + "vfe1_fast_ahb",
>> + "vfe_lite",
>> + "vfe_lite_ahb",
>> + "vfe_lite_cphy_rx",
>> + "vfe_lite_csid";
>> +
>> + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
>> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-names = "csid0",
>> + "csid1",
>> + "csid_lite0",
>> + "csid_lite1",
>> + "csid_lite2",
>> + "csid_lite3",
>> + "csid_lite4",
>> + "csiphy0",
>> + "csiphy1",
>> + "csiphy2",
>> + "csiphy3",
>> + "tpg0",
>> + "tpg1",
>> + "tpg2",
>> + "vfe0",
>> + "vfe1",
>> + "vfe_lite0",
>> + "vfe_lite1",
>> + "vfe_lite2",
>> + "vfe_lite3",
>> + "vfe_lite4";
>> +
>> + interconnects = <&gem_noc MASTER_APPSS_PROC
>> QCOM_ICC_TAG_ACTIVE_ONLY
>> + &config_noc SLAVE_CAMERA_CFG
>> QCOM_ICC_TAG_ACTIVE_ONLY>,
>> + <&mmss_noc MASTER_CAMNOC_HF
>> QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "ahb",
>> + "hf_0";
>> +
>> + iommus = <&apps_smmu 0x3400 0x20>;
>> +
>> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
>> + power-domain-names = "top";
>> +
>> + vdda-phy-supply = <&vreg_l4a_0p88>;
>> + vdda-pll-supply = <&vreg_l1c_1p2>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> + };
>> + };
>
> Otherwise that this looks fine, please fix and then add.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 4/9] arm64: dts: qcom: sa8775p: Add support for camss
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
` (2 preceding siblings ...)
2025-07-03 17:19 ` [PATCH v3 3/9] media: dt-bindings: Add qcom,sa8775p-camss compatible Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 13:48 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 5/9] media: qcom: camss: Add sa8775p compatible Vikram Sharma
` (4 subsequent siblings)
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio
Add changes to support the camera subsystem on the SA8775P.
Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 185 ++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index fed34717460f..38ac33b082c8 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
+#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
@@ -4345,6 +4346,190 @@ videocc: clock-controller@abf0000 {
#power-domain-cells = <1>;
};
+ camss: isp@ac7a000 {
+ compatible = "qcom,sa8775p-camss";
+
+ reg = <0x0 0xac7a000 0x0 0x0f00>,
+ <0x0 0xac7c000 0x0 0x0f00>,
+ <0x0 0xac84000 0x0 0x0f00>,
+ <0x0 0xac88000 0x0 0x0f00>,
+ <0x0 0xac8c000 0x0 0x0f00>,
+ <0x0 0xac90000 0x0 0x0f00>,
+ <0x0 0xac94000 0x0 0x0f00>,
+ <0x0 0xac78000 0x0 0x1000>,
+ <0x0 0xac9c000 0x0 0x2000>,
+ <0x0 0xac9e000 0x0 0x2000>,
+ <0x0 0xaca0000 0x0 0x2000>,
+ <0x0 0xaca2000 0x0 0x2000>,
+ <0x0 0xacac000 0x0 0x0400>,
+ <0x0 0xacad000 0x0 0x0400>,
+ <0x0 0xacae000 0x0 0x0400>,
+ <0x0 0xac4d000 0x0 0xd000>,
+ <0x0 0xac5a000 0x0 0xd000>,
+ <0x0 0xac85000 0x0 0x0d00>,
+ <0x0 0xac89000 0x0 0x0d00>,
+ <0x0 0xac8d000 0x0 0x0d00>,
+ <0x0 0xac91000 0x0 0x0d00>,
+ <0x0 0xac95000 0x0 0x0d00>;
+ reg-names = "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csid_wrapper",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb_clk",
+ "cpas_vfe_lite",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "csid",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy_rx",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "icp_ahb",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid_lite0",
+ "csid_lite1",
+ "csid_lite2",
+ "csid_lite3",
+ "csid_lite4",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "tpg0",
+ "tpg1",
+ "tpg2",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe_lite2",
+ "vfe_lite3",
+ "vfe_lite4";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_0";
+
+ iommus = <&apps_smmu 0x3400 0x20>;
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,sa8775p-camcc";
reg = <0x0 0x0ade0000 0x0 0x20000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 4/9] arm64: dts: qcom: sa8775p: Add support for camss
2025-07-03 17:19 ` [PATCH v3 4/9] arm64: dts: qcom: sa8775p: Add support for camss Vikram Sharma
@ 2025-07-28 13:48 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 13:48 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel, Konrad Dybcio
On 03/07/2025 18:19, Vikram Sharma wrote:
> Add changes to support the camera subsystem on the SA8775P.
>
> Co-developed-by: Suresh Vankadara<quic_svankada@quicinc.com>
> Signed-off-by: Suresh Vankadara<quic_svankada@quicinc.com>
> Signed-off-by: Vikram Sharma<quic_vikramsa@quicinc.com>
> Reviewed-by: Konrad Dybcio<konrad.dybcio@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 185 ++++++++++++++++++++++++++
> 1 file changed, 185 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index fed34717460f..38ac33b082c8 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -12,6 +12,7 @@
> #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
> #include <dt-bindings/clock/qcom,sa8775p-videocc.h>
> +#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> #include <dt-bindings/dma/qcom-gpi.h>
> #include <dt-bindings/interconnect/qcom,osm-l3.h>
> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
> @@ -4345,6 +4346,190 @@ videocc: clock-controller@abf0000 {
> #power-domain-cells = <1>;
> };
>
> + camss: isp@ac7a000 {
> + compatible = "qcom,sa8775p-camss";
> +
> + reg = <0x0 0xac7a000 0x0 0x0f00>,
> + <0x0 0xac7c000 0x0 0x0f00>,
> + <0x0 0xac84000 0x0 0x0f00>,
> + <0x0 0xac88000 0x0 0x0f00>,
> + <0x0 0xac8c000 0x0 0x0f00>,
> + <0x0 0xac90000 0x0 0x0f00>,
> + <0x0 0xac94000 0x0 0x0f00>,
> + <0x0 0xac78000 0x0 0x1000>,
> + <0x0 0xac9c000 0x0 0x2000>,
> + <0x0 0xac9e000 0x0 0x2000>,
> + <0x0 0xaca0000 0x0 0x2000>,
> + <0x0 0xaca2000 0x0 0x2000>,
> + <0x0 0xacac000 0x0 0x0400>,
> + <0x0 0xacad000 0x0 0x0400>,
> + <0x0 0xacae000 0x0 0x0400>,
> + <0x0 0xac4d000 0x0 0xd000>,
> + <0x0 0xac5a000 0x0 0xd000>,
> + <0x0 0xac85000 0x0 0x0d00>,
> + <0x0 0xac89000 0x0 0x0d00>,
> + <0x0 0xac8d000 0x0 0x0d00>,
> + <0x0 0xac91000 0x0 0x0d00>,
> + <0x0 0xac95000 0x0 0x0d00>;
> + reg-names = "csid0",
> + "csid1",
> + "csid_lite0",
> + "csid_lite1",
> + "csid_lite2",
> + "csid_lite3",
> + "csid_lite4",
> + "csid_wrapper",
You can add my RB here with csid_wrapper as the first register bank.
The reason for this is CSID wrapper contains a mux for the CSID register
banks and so its the "boss" so to speak.
Please update and then add my.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 5/9] media: qcom: camss: Add sa8775p compatible
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
` (3 preceding siblings ...)
2025-07-03 17:19 ` [PATCH v3 4/9] arm64: dts: qcom: sa8775p: Add support for camss Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 13:49 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 6/9] media: qcom: camss: Add support for CSIPHY 690 Vikram Sharma
` (3 subsequent siblings)
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel
Add CAMSS_8775P enum, SA8775P compatible and sa8775p camss driver
private data, the private data just include some basic information
now, later changes will enumerate with csiphy, tpg, csid and vfe
resources.
Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
drivers/media/platform/qcom/camss/camss.c | 23 +++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 310b5cd8de5f..3122a29891c2 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2483,6 +2483,19 @@ static const struct resources_icc icc_res_sm8550[] = {
},
};
+static const struct resources_icc icc_res_sa8775p[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 38400,
+ .icc_bw_tbl.peak = 76800,
+ },
+ {
+ .name = "hf_0",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
/* CSIPHY0 */
{
@@ -3753,6 +3766,15 @@ static const struct camss_resources msm8996_resources = {
.link_entities = camss_link_entities
};
+
+static const struct camss_resources sa8775p_resources = {
+ .version = CAMSS_8775P,
+ .pd_name = "top",
+ .icc_res = icc_res_sa8775p,
+ .icc_path_num = ARRAY_SIZE(icc_res_sa8775p),
+ .link_entities = camss_link_entities
+};
+
static const struct camss_resources sdm660_resources = {
.version = CAMSS_660,
.csiphy_res = csiphy_res_660,
@@ -3865,6 +3887,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,sa8775p-camss", .data = &sa8775p_resources },
{ .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 63c0afee154a..345479f6feba 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -86,6 +86,7 @@ enum camss_version {
CAMSS_8280XP,
CAMSS_845,
CAMSS_8550,
+ CAMSS_8775P,
CAMSS_X1E80100,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 5/9] media: qcom: camss: Add sa8775p compatible
2025-07-03 17:19 ` [PATCH v3 5/9] media: qcom: camss: Add sa8775p compatible Vikram Sharma
@ 2025-07-28 13:49 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 13:49 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 03/07/2025 18:19, Vikram Sharma wrote:
> Add CAMSS_8775P enum, SA8775P compatible and sa8775p camss driver
> private data, the private data just include some basic information
> now, later changes will enumerate with csiphy, tpg, csid and vfe
> resources.
>
> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> drivers/media/platform/qcom/camss/camss.c | 23 +++++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 310b5cd8de5f..3122a29891c2 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2483,6 +2483,19 @@ static const struct resources_icc icc_res_sm8550[] = {
> },
> };
>
> +static const struct resources_icc icc_res_sa8775p[] = {
> + {
> + .name = "ahb",
> + .icc_bw_tbl.avg = 38400,
> + .icc_bw_tbl.peak = 76800,
> + },
> + {
> + .name = "hf_0",
> + .icc_bw_tbl.avg = 2097152,
> + .icc_bw_tbl.peak = 2097152,
> + },
> +};
> +
> static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
> /* CSIPHY0 */
> {
> @@ -3753,6 +3766,15 @@ static const struct camss_resources msm8996_resources = {
> .link_entities = camss_link_entities
> };
>
> +
> +static const struct camss_resources sa8775p_resources = {
> + .version = CAMSS_8775P,
> + .pd_name = "top",
> + .icc_res = icc_res_sa8775p,
> + .icc_path_num = ARRAY_SIZE(icc_res_sa8775p),
> + .link_entities = camss_link_entities
> +};
> +
> static const struct camss_resources sdm660_resources = {
> .version = CAMSS_660,
> .csiphy_res = csiphy_res_660,
> @@ -3865,6 +3887,7 @@ static const struct of_device_id camss_dt_match[] = {
> { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
> { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
> { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
> + { .compatible = "qcom,sa8775p-camss", .data = &sa8775p_resources },
> { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
> { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
> { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
> index 63c0afee154a..345479f6feba 100644
> --- a/drivers/media/platform/qcom/camss/camss.h
> +++ b/drivers/media/platform/qcom/camss/camss.h
> @@ -86,6 +86,7 @@ enum camss_version {
> CAMSS_8280XP,
> CAMSS_845,
> CAMSS_8550,
> + CAMSS_8775P,
> CAMSS_X1E80100,
> };
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 6/9] media: qcom: camss: Add support for CSIPHY 690
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
` (4 preceding siblings ...)
2025-07-03 17:19 ` [PATCH v3 5/9] media: qcom: camss: Add sa8775p compatible Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 13:51 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 7/9] media: qcom: camss: Add support for CSID for sa8775p Vikram Sharma
` (2 subsequent siblings)
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel, Wenmeng Liu
Add support for CSIPHY found on SA8775P (Titan 690).
This implementation is based on the titan 690 implementation.
Co-developed-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
.../qcom/camss/camss-csiphy-3ph-1-0.c | 84 +++++++++++++++++++
.../media/platform/qcom/camss/camss-csiphy.c | 5 ++
.../media/platform/qcom/camss/camss-csiphy.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 75 +++++++++++++++++
4 files changed, 165 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index f732a76de93e..bb5ebaa13ec8 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -64,6 +64,85 @@ struct csiphy_lane_regs {
u32 csiphy_param_type;
};
+/* GEN2 1.3.0 2PH */
+static const struct
+csiphy_lane_regs lane_regs_sa8775p[] = {
+ {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x005C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0060, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x025C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0260, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x045C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0460, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x065C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0660, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
/* GEN2 1.0 2PH */
static const struct
csiphy_lane_regs lane_regs_sdm845[] = {
@@ -749,6 +828,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_8280XP:
case CAMSS_845:
case CAMSS_8550:
+ case CAMSS_8775P:
case CAMSS_X1E80100:
ret = true;
break;
@@ -848,6 +928,10 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
regs->offset = 0x1000;
break;
+ case CAMSS_8775P:
+ regs->lane_regs = &lane_regs_sa8775p[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
+ break;
default:
WARN(1, "unknown csiphy version\n");
return -ENODEV;
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index c622efcc92ff..f6a2ac385953 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = {
.formats = formats_8x96
};
+const struct csiphy_formats csiphy_formats_sa8775p = {
+ .nformats = ARRAY_SIZE(formats_sdm845),
+ .formats = formats_sdm845
+};
+
const struct csiphy_formats csiphy_formats_sc7280 = {
.nformats = ARRAY_SIZE(formats_sdm845),
.formats = formats_sdm845
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
index ab91273303b9..842e72b74ce4 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.h
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
@@ -126,6 +126,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
extern const struct csiphy_formats csiphy_formats_8x16;
extern const struct csiphy_formats csiphy_formats_8x96;
+extern const struct csiphy_formats csiphy_formats_sa8775p;
extern const struct csiphy_formats csiphy_formats_sc7280;
extern const struct csiphy_formats csiphy_formats_sdm845;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 3122a29891c2..ebc3b296bb50 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2483,6 +2483,81 @@ static const struct resources_icc icc_res_sm8550[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_8775p[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy_rx", "csiphy0", "csiphy0_timer"},
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sa8775p
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy_rx", "csiphy1", "csiphy1_timer"},
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sa8775p
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy_rx", "csiphy2", "csiphy2_timer"},
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sa8775p
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+
+ .clock = { "csiphy_rx", "csiphy3", "csiphy3_timer"},
+ .clock_rate = {
+ { 400000000 },
+ { 0 },
+ { 400000000 },
+ },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sa8775p
+ }
+ },
+};
+
static const struct resources_icc icc_res_sa8775p[] = {
{
.name = "ahb",
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 6/9] media: qcom: camss: Add support for CSIPHY 690
2025-07-03 17:19 ` [PATCH v3 6/9] media: qcom: camss: Add support for CSIPHY 690 Vikram Sharma
@ 2025-07-28 13:51 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 13:51 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel, Wenmeng Liu
On 03/07/2025 18:19, Vikram Sharma wrote:
> Add support for CSIPHY found on SA8775P (Titan 690).
> This implementation is based on the titan 690 implementation.
>
> Co-developed-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
> Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> .../qcom/camss/camss-csiphy-3ph-1-0.c | 84 +++++++++++++++++++
> .../media/platform/qcom/camss/camss-csiphy.c | 5 ++
> .../media/platform/qcom/camss/camss-csiphy.h | 1 +
> drivers/media/platform/qcom/camss/camss.c | 75 +++++++++++++++++
> 4 files changed, 165 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index f732a76de93e..bb5ebaa13ec8 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -64,6 +64,85 @@ struct csiphy_lane_regs {
> u32 csiphy_param_type;
> };
>
> +/* GEN2 1.3.0 2PH */
I'd be nice to include the process node number here. Its not a secret so
please add for the edifcation of the reader.
> +static const struct
> +csiphy_lane_regs lane_regs_sa8775p[] = {
> + {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
> + {0x005C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0060, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x025C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0260, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x045C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0460, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x065C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0660, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
> + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
> +};
> +
> /* GEN2 1.0 2PH */
> static const struct
> csiphy_lane_regs lane_regs_sdm845[] = {
> @@ -749,6 +828,7 @@ static bool csiphy_is_gen2(u32 version)
> case CAMSS_8280XP:
> case CAMSS_845:
> case CAMSS_8550:
> + case CAMSS_8775P:
> case CAMSS_X1E80100:
> ret = true;
> break;
> @@ -848,6 +928,10 @@ static int csiphy_init(struct csiphy_device *csiphy)
> regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
> regs->offset = 0x1000;
> break;
> + case CAMSS_8775P:
> + regs->lane_regs = &lane_regs_sa8775p[0];
> + regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
> + break;
> default:
> WARN(1, "unknown csiphy version\n");
> return -ENODEV;
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
> index c622efcc92ff..f6a2ac385953 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
> @@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = {
> .formats = formats_8x96
> };
>
> +const struct csiphy_formats csiphy_formats_sa8775p = {
> + .nformats = ARRAY_SIZE(formats_sdm845),
> + .formats = formats_sdm845
> +};
> +
> const struct csiphy_formats csiphy_formats_sc7280 = {
> .nformats = ARRAY_SIZE(formats_sdm845),
> .formats = formats_sdm845
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h
> index ab91273303b9..842e72b74ce4 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy.h
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h
> @@ -126,6 +126,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
>
> extern const struct csiphy_formats csiphy_formats_8x16;
> extern const struct csiphy_formats csiphy_formats_8x96;
> +extern const struct csiphy_formats csiphy_formats_sa8775p;
> extern const struct csiphy_formats csiphy_formats_sc7280;
> extern const struct csiphy_formats csiphy_formats_sdm845;
>
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 3122a29891c2..ebc3b296bb50 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2483,6 +2483,81 @@ static const struct resources_icc icc_res_sm8550[] = {
> },
> };
>
> +static const struct camss_subdev_resources csiphy_res_8775p[] = {
> + /* CSIPHY0 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
Drop the dead newline please.
> + .clock = { "csiphy_rx", "csiphy0", "csiphy0_timer"},
> + .clock_rate = {
> + { 400000000 },
> + { 0 },
> + { 400000000 },
> + },
> + .reg = { "csiphy0" },
> + .interrupt = { "csiphy0" },
> + .csiphy = {
> + .id = 0,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sa8775p
> + }
> + },
> + /* CSIPHY1 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy_rx", "csiphy1", "csiphy1_timer"},
> + .clock_rate = {
> + { 400000000 },
> + { 0 },
> + { 400000000 },
> + },
> + .reg = { "csiphy1" },
> + .interrupt = { "csiphy1" },
> + .csiphy = {
> + .id = 1,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sa8775p
> + }
> + },
> + /* CSIPHY2 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy_rx", "csiphy2", "csiphy2_timer"},
> + .clock_rate = {
> + { 400000000 },
> + { 0 },
> + { 400000000 },
> + },
> + .reg = { "csiphy2" },
> + .interrupt = { "csiphy2" },
> + .csiphy = {
> + .id = 2,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sa8775p
> + }
> + },
> + /* CSIPHY3 */
> + {
> + .regulators = { "vdda-phy", "vdda-pll" },
> +
> + .clock = { "csiphy_rx", "csiphy3", "csiphy3_timer"},
> + .clock_rate = {
> + { 400000000 },
> + { 0 },
> + { 400000000 },
> + },
> + .reg = { "csiphy3" },
> + .interrupt = { "csiphy3" },
> + .csiphy = {
> + .id = 3,
> + .hw_ops = &csiphy_ops_3ph_1_0,
> + .formats = &csiphy_formats_sa8775p
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_sa8775p[] = {
> {
> .name = "ahb",
Assuming that's done:
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 7/9] media: qcom: camss: Add support for CSID for sa8775p
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
` (5 preceding siblings ...)
2025-07-03 17:19 ` [PATCH v3 6/9] media: qcom: camss: Add support for CSIPHY 690 Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 14:02 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690 Vikram Sharma
2025-07-03 17:19 ` [PATCH v3 9/9] media: qcom: camss: Enumerate resources for SA8775P Vikram Sharma
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel
The CSID in sa8775p is version 690, This csid is different from
csid 780 w.r.t few bit-fields.
Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
.../platform/qcom/camss/camss-csid-gen3.c | 31 +++-
drivers/media/platform/qcom/camss/camss.c | 151 ++++++++++++++++++
2 files changed, 175 insertions(+), 7 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
index 0941152ec301..f62084fb8287 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
@@ -47,8 +47,12 @@
#define CSID_CSI2_RX_IRQ_CLEAR 0xA4
#define CSID_CSI2_RX_IRQ_SET 0xA8
+#define IS_CSID_690(csid) (csid->camss->res->version ==\
+ CAMSS_8775P ? true : false)
#define CSID_BUF_DONE_IRQ_STATUS 0x8C
-#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 14)
+#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ?\
+ 1 : (IS_CSID_690(csid) ?\
+ 13 : 14))
#define CSID_BUF_DONE_IRQ_MASK 0x90
#define CSID_BUF_DONE_IRQ_CLEAR 0x94
#define CSID_BUF_DONE_IRQ_SET 0x98
@@ -61,6 +65,7 @@
#define CSID_CSI2_RX_CFG0 0x200
#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
+#define CSI2_RX_CFG0_VC_MODE 3
#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
#define CSI2_RX_CFG0_PHY_NUM_SEL 20
@@ -68,7 +73,9 @@
#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
#define CSI2_RX_CFG1_VC_MODE BIT(2)
-#define CSID_RDI_CFG0(rdi) (0x500 + 0x100 * (rdi))
+#define CSID_RDI_CFG0(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
+ (0x300 + 0x100 * (rdi)) :\
+ (0x500 + 0x100 * (rdi)))
#define RDI_CFG0_TIMESTAMP_EN BIT(6)
#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
#define RDI_CFG0_DECODE_FORMAT 12
@@ -77,10 +84,14 @@
#define RDI_CFG0_DT_ID 27
#define RDI_CFG0_EN BIT(31)
-#define CSID_RDI_CTRL(rdi) (0x504 + 0x100 * (rdi))
+#define CSID_RDI_CTRL(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
+ (0x304 + 0x100 * (rdi)) :\
+ (0x504 + 0x100 * (rdi)))
#define RDI_CTRL_START_CMD BIT(0)
-#define CSID_RDI_CFG1(rdi) (0x510 + 0x100 * (rdi))
+#define CSID_RDI_CFG1(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
+ (0x310 + 0x100 * (rdi)) :\
+ (0x510 + 0x100 * (rdi)))
#define RDI_CFG1_DROP_H_EN BIT(5)
#define RDI_CFG1_DROP_V_EN BIT(6)
#define RDI_CFG1_CROP_H_EN BIT(7)
@@ -88,9 +99,12 @@
#define RDI_CFG1_PIX_STORE BIT(10)
#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
-#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi))
-#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54C + 0x100 * (rdi))
-
+#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
+ (0x348 + 0x100 * (rdi)) :\
+ (0x548 + 0x100 * (rdi)))
+#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
+ (0x34C + 0x100 * (rdi)) :\
+ (0x54C + 0x100 * (rdi)))
#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
static void __csid_configure_rx(struct csid_device *csid,
@@ -102,6 +116,9 @@ static void __csid_configure_rx(struct csid_device *csid,
val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL;
+ if (IS_CSID_690(csid) && (vc > 3))
+ val |= 1 << CSI2_RX_CFG0_VC_MODE;
+
writel(val, csid->base + CSID_CSI2_RX_CFG0);
val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index ebc3b296bb50..b2398196b9ff 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2269,6 +2269,10 @@ static const struct camss_subdev_resources csiphy_res_8550[] = {
}
};
+static const struct resources_wrapper csid_wrapper_res_sa8775p = {
+ .reg = "csid_wrapper",
+};
+
static const struct resources_wrapper csid_wrapper_res_sm8550 = {
.reg = "csid_wrapper",
};
@@ -2558,6 +2562,153 @@ static const struct camss_subdev_resources csiphy_res_8775p[] = {
},
};
+static const struct camss_subdev_resources csid_res_8775p[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+
+ .clock = { "csid", "csiphy_rx"},
+ .clock_rate = {
+ { 400000000, 400000000},
+ { 400000000, 400000000}
+ },
+
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+
+ .clock = { "csid", "csiphy_rx"},
+ .clock_rate = {
+ { 400000000, 400000000},
+ { 400000000, 400000000}
+ },
+
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+
+ /* CSID2 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 400000000, 400000000, 0},
+ { 0, 0, 400000000, 480000000, 0}
+ },
+
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID3 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 400000000, 400000000, 0},
+ { 0, 0, 400000000, 480000000, 0}
+ },
+
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID4 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 400000000, 400000000, 0},
+ { 0, 0, 400000000, 480000000, 0}
+ },
+
+ .reg = { "csid_lite2" },
+ .interrupt = { "csid_lite2" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID5 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 400000000, 400000000, 0},
+ { 0, 0, 400000000, 480000000, 0}
+ },
+
+ .reg = { "csid_lite3" },
+ .interrupt = { "csid_lite3" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID6 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 400000000, 400000000, 0},
+ { 0, 0, 400000000, 480000000, 0}
+ },
+
+ .reg = { "csid_lite4" },
+ .interrupt = { "csid_lite4" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen3,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+};
+
static const struct resources_icc icc_res_sa8775p[] = {
{
.name = "ahb",
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 7/9] media: qcom: camss: Add support for CSID for sa8775p
2025-07-03 17:19 ` [PATCH v3 7/9] media: qcom: camss: Add support for CSID for sa8775p Vikram Sharma
@ 2025-07-28 14:02 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 14:02 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 03/07/2025 18:19, Vikram Sharma wrote:
> The CSID in sa8775p is version 690, This csid is different from
> csid 780 w.r.t few bit-fields.
>
> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> .../platform/qcom/camss/camss-csid-gen3.c | 31 +++-
> drivers/media/platform/qcom/camss/camss.c | 151 ++++++++++++++++++
> 2 files changed, 175 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
> index 0941152ec301..f62084fb8287 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c
> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
> @@ -47,8 +47,12 @@
> #define CSID_CSI2_RX_IRQ_CLEAR 0xA4
> #define CSID_CSI2_RX_IRQ_SET 0xA8
>
> +#define IS_CSID_690(csid) (csid->camss->res->version ==\
> + CAMSS_8775P ? true : false)
You don't need to make this into a bool.
version == CAMSS_8775P will do exactly the same logical thing.
> #define CSID_BUF_DONE_IRQ_STATUS 0x8C
> -#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 14)
> +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ?\
> + 1 : (IS_CSID_690(csid) ?\
> + 13 : 14))
> #define CSID_BUF_DONE_IRQ_MASK 0x90
> #define CSID_BUF_DONE_IRQ_CLEAR 0x94
> #define CSID_BUF_DONE_IRQ_SET 0x98
> @@ -61,6 +65,7 @@
>
> #define CSID_CSI2_RX_CFG0 0x200
> #define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
> +#define CSI2_RX_CFG0_VC_MODE 3
> #define CSI2_RX_CFG0_DL0_INPUT_SEL 4
> #define CSI2_RX_CFG0_PHY_NUM_SEL 20
>
> @@ -68,7 +73,9 @@
> #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
> #define CSI2_RX_CFG1_VC_MODE BIT(2)
>
> -#define CSID_RDI_CFG0(rdi) (0x500 + 0x100 * (rdi))
> +#define CSID_RDI_CFG0(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
> + (0x300 + 0x100 * (rdi)) :\
> + (0x500 + 0x100 * (rdi)))
> #define RDI_CFG0_TIMESTAMP_EN BIT(6)
> #define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
> #define RDI_CFG0_DECODE_FORMAT 12
> @@ -77,10 +84,14 @@
> #define RDI_CFG0_DT_ID 27
> #define RDI_CFG0_EN BIT(31)
>
> -#define CSID_RDI_CTRL(rdi) (0x504 + 0x100 * (rdi))
> +#define CSID_RDI_CTRL(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
> + (0x304 + 0x100 * (rdi)) :\
> + (0x504 + 0x100 * (rdi)))
> #define RDI_CTRL_START_CMD BIT(0)
>
> -#define CSID_RDI_CFG1(rdi) (0x510 + 0x100 * (rdi))
> +#define CSID_RDI_CFG1(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
> + (0x310 + 0x100 * (rdi)) :\
> + (0x510 + 0x100 * (rdi)))
> #define RDI_CFG1_DROP_H_EN BIT(5)
> #define RDI_CFG1_DROP_V_EN BIT(6)
> #define RDI_CFG1_CROP_H_EN BIT(7)
> @@ -88,9 +99,12 @@
> #define RDI_CFG1_PIX_STORE BIT(10)
> #define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
>
> -#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi))
> -#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54C + 0x100 * (rdi))
> -
> +#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
> + (0x348 + 0x100 * (rdi)) :\
> + (0x548 + 0x100 * (rdi)))
> +#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (csid_is_lite(csid) && IS_CSID_690(csid) ?\
> + (0x34C + 0x100 * (rdi)) :\
> + (0x54C + 0x100 * (rdi)))
> #define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1
>
> static void __csid_configure_rx(struct csid_device *csid,
> @@ -102,6 +116,9 @@ static void __csid_configure_rx(struct csid_device *csid,
> val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
> val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL;
>
> + if (IS_CSID_690(csid) && (vc > 3))
> + val |= 1 << CSI2_RX_CFG0_VC_MODE;
> +
I remeber that the > 3 has a purpose but, I don't remember of off the
top of my head what that is.
Please add a comment to state why "> 3" matters.
BTW should this be "> 3" or ">= 3" please double check.
> writel(val, csid->base + CSID_CSI2_RX_CFG0);
>
> val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index ebc3b296bb50..b2398196b9ff 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2269,6 +2269,10 @@ static const struct camss_subdev_resources csiphy_res_8550[] = {
> }
> };
>
> +static const struct resources_wrapper csid_wrapper_res_sa8775p = {
> + .reg = "csid_wrapper",
> +};
> +
> static const struct resources_wrapper csid_wrapper_res_sm8550 = {
> .reg = "csid_wrapper",
> };
Redefining the same string in separate structures over and over again
seems wasteful.
Please take the opporunity of this new addition to rationalise down the
string declarations and .. if possible the number of struct
resources_wrappers we are doing here.
> @@ -2558,6 +2562,153 @@ static const struct camss_subdev_resources csiphy_res_8775p[] = {
> },
> };
>
> +static const struct camss_subdev_resources csid_res_8775p[] = {
> + /* CSID0 */
> + {
> + .regulators = {},
> +
Zap the newlines.
> + .clock = { "csid", "csiphy_rx"},
> + .clock_rate = {
> + { 400000000, 400000000},
> + { 400000000, 400000000}
> + },
> +
> + .reg = { "csid0" },
> + .interrupt = { "csid0" },
> + .csid = {
> + .is_lite = false,
> + .hw_ops = &csid_ops_gen3,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID1 */
> + {
> + .regulators = {},
> +
> + .clock = { "csid", "csiphy_rx"},
> + .clock_rate = {
> + { 400000000, 400000000},
> + { 400000000, 400000000}
> + },
> +
> + .reg = { "csid1" },
> + .interrupt = { "csid1" },
> + .csid = {
> + .is_lite = false,
> + .hw_ops = &csid_ops_gen3,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> +
> + /* CSID2 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 400000000, 400000000, 0},
> + { 0, 0, 400000000, 480000000, 0}
> + },
> +
> + .reg = { "csid_lite0" },
> + .interrupt = { "csid_lite0" },
> + .csid = {
> + .is_lite = true,
> + .hw_ops = &csid_ops_gen3,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID3 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 400000000, 400000000, 0},
> + { 0, 0, 400000000, 480000000, 0}
> + },
> +
> + .reg = { "csid_lite1" },
> + .interrupt = { "csid_lite1" },
> + .csid = {
> + .is_lite = true,
> + .hw_ops = &csid_ops_gen3,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID4 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 400000000, 400000000, 0},
> + { 0, 0, 400000000, 480000000, 0}
> + },
> +
> + .reg = { "csid_lite2" },
> + .interrupt = { "csid_lite2" },
> + .csid = {
> + .is_lite = true,
> + .hw_ops = &csid_ops_gen3,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID5 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 400000000, 400000000, 0},
> + { 0, 0, 400000000, 480000000, 0}
> + },
> +
> + .reg = { "csid_lite3" },
> + .interrupt = { "csid_lite3" },
> + .csid = {
> + .is_lite = true,
> + .hw_ops = &csid_ops_gen3,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID6 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 400000000, 400000000, 0},
> + { 0, 0, 400000000, 480000000, 0}
> + },
> +
> + .reg = { "csid_lite4" },
> + .interrupt = { "csid_lite4" },
> + .csid = {
> + .is_lite = true,
> + .hw_ops = &csid_ops_gen3,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .formats = &csid_formats_gen2
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_sa8775p[] = {
> {
> .name = "ahb",
---
bod
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
` (6 preceding siblings ...)
2025-07-03 17:19 ` [PATCH v3 7/9] media: qcom: camss: Add support for CSID for sa8775p Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 14:10 ` Bryan O'Donoghue
2025-09-01 9:04 ` Bryan O'Donoghue
2025-07-03 17:19 ` [PATCH v3 9/9] media: qcom: camss: Enumerate resources for SA8775P Vikram Sharma
8 siblings, 2 replies; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel
Add support for VFE found on SA8775P (Titan 690). This VFE is
different from vfe 780 w.r.t few register offsets.
It supports two full and five lite VFE.
Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
.../platform/qcom/camss/camss-vfe-gen3.c | 67 +++++--
drivers/media/platform/qcom/camss/camss-vfe.c | 5 +-
drivers/media/platform/qcom/camss/camss.c | 189 ++++++++++++++++++
3 files changed, 242 insertions(+), 19 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen3.c b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
index 93d16b0951e9..a5eddc8c76ae 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen3
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen2 (SA8755P/SM8550)
*
* Copyright (c) 2024 Qualcomm Technologies, Inc.
*/
@@ -12,13 +12,41 @@
#include "camss.h"
#include "camss-vfe.h"
-#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00)
+#define IS_VFE_690(vfe) \
+ (vfe->camss->res->version == CAMSS_8775P ? true : false)
+
+#define BUS_REG_BASE_690 \
+ (vfe_is_lite(vfe) ? 0x480 : 0x400)
+#define BUS_REG_BASE_780 \
+ (vfe_is_lite(vfe) ? 0x200 : 0xC00)
+#define BUS_REG_BASE \
+ (IS_VFE_690(vfe) ? BUS_REG_BASE_690 : BUS_REG_BASE_780)
+
+#define VFE_TOP_CORE_CFG (0x24)
+
+#define VFE_BUS_WM_TEST_BUS_CTRL_690 (BUS_REG_BASE + 0xFC)
+#define VFE_BUS_WM_TEST_BUS_CTRL_780 (BUS_REG_BASE + 0xDC)
+#define VFE_BUS_WM_TEST_BUS_CTRL \
+ (IS_VFE_690(vfe) ? VFE_BUS_WM_TEST_BUS_CTRL_690 \
+ : VFE_BUS_WM_TEST_BUS_CTRL_780)
+/*
+ * Bus client mapping:
+ *
+ * Full VFE:
+ * VFE_690: 16 = RDI0, 17 = RDI1, 18 = RDI2
+ * VFE_780: 23 = RDI0, 24 = RDI1, 25 = RDI2
+ *
+ * VFE LITE:
+ * VFE_690 : 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5
+ * VFE_780 : 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4
+ */
+#define RDI_WM_690(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n))
+#define RDI_WM_780(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
+#define RDI_WM(n) (IS_VFE_690(vfe) ? RDI_WM_690(n) : RDI_WM_780(n))
#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
-#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC)
-
#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100)
#define WM_CFG_EN BIT(0)
#define WM_VIR_FRM_EN BIT(1)
@@ -39,17 +67,6 @@
#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100)
#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100)
-/*
- * Bus client mapping:
- *
- * Full VFE:
- * 23 = RDI0, 24 = RDI1, 25 = RDI2
- *
- * VFE LITE:
- * 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4
- */
-#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
-
static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
{
struct v4l2_pix_format_mplane *pix =
@@ -62,14 +79,23 @@ static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
- writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
- vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
+ if (IS_VFE_690(vfe))
+ writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height,
+ vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
+ else
+ writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
+ vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
+
writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
+ /* TOP CORE CFG */
+ if (IS_VFE_690(vfe))
+ writel(0x600000, vfe->base + VFE_TOP_CORE_CFG);
+
/* no dropped frames, one irq per frame */
writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
@@ -92,7 +118,12 @@ static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
struct vfe_line *line)
{
wm = RDI_WM(wm);
- writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
+
+ if (IS_VFE_690(vfe))
+ writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
+ else
+ writel((addr >> 8) & 0xFFFFFFFF, vfe->base +
+ VFE_BUS_WM_IMAGE_ADDR(wm));
dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n",
wm, addr);
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 4bca6c3abaff..99cbe09343f2 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8280XP:
case CAMSS_845:
case CAMSS_8550:
+ case CAMSS_8775P:
case CAMSS_X1E80100:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
@@ -910,7 +911,8 @@ static int vfe_match_clock_names(struct vfe_device *vfe,
return (!strcmp(clock->name, vfe_name) ||
!strcmp(clock->name, vfe_lite_name) ||
- !strcmp(clock->name, "vfe_lite"));
+ !strcmp(clock->name, "vfe_lite") ||
+ !strcmp(clock->name, "camnoc_axi"));
}
/*
@@ -1974,6 +1976,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
case CAMSS_8280XP:
case CAMSS_845:
case CAMSS_8550:
+ case CAMSS_8775P:
case CAMSS_X1E80100:
ret = 16;
break;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index b2398196b9ff..3a11c0a98eb1 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2709,6 +2709,195 @@ static const struct camss_subdev_resources csid_res_8775p[] = {
},
};
+static const struct camss_subdev_resources vfe_res_8775p[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb",
+ "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf",
+ "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi",
+ "icp_ahb"},
+ .clock_rate = {
+ { 0 },
+ { 480000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 0 },
+ { 0, 80000000 },
+ { 300000000, 400000000 },
+ { 400000000 },
+ { 0 },
+ },
+
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = false,
+ .pd_name = NULL,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb",
+ "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf",
+ "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi",
+ "icp_ahb"},
+ .clock_rate = {
+ { 0 },
+ { 480000000 },
+ { 300000000, 400000000 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 0 },
+ { 0, 80000000 },
+ { 300000000, 400000000 },
+ { 400000000 },
+ { 0 },
+ },
+
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .has_pd = false,
+ .pd_name = NULL,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 0, 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 0, 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE4 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 0, 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ },
+ .reg = { "vfe_lite2" },
+ .interrupt = { "vfe_lite2" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE5 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 0, 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ },
+ .reg = { "vfe_lite3" },
+ .interrupt = { "vfe_lite3" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE6 (lite) */
+ {
+ .regulators = {},
+
+ .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
+ "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "vfe_lite"},
+ .clock_rate = {
+ { 0, 0, 0, 0 },
+ { 300000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 400000000, 400000000, 400000000, 400000000 },
+ { 480000000, 600000000, 600000000, 600000000 },
+ },
+ .reg = { "vfe_lite4" },
+ .interrupt = { "vfe_lite4" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .hw_ops = &vfe_ops_gen3,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
static const struct resources_icc icc_res_sa8775p[] = {
{
.name = "ahb",
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690
2025-07-03 17:19 ` [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690 Vikram Sharma
@ 2025-07-28 14:10 ` Bryan O'Donoghue
2025-09-01 9:04 ` Bryan O'Donoghue
1 sibling, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 14:10 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 03/07/2025 18:19, Vikram Sharma wrote:
> Add support for VFE found on SA8775P (Titan 690). This VFE is
> different from vfe 780 w.r.t few register offsets.
> It supports two full and five lite VFE.
>
> Co-developed-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> .../platform/qcom/camss/camss-vfe-gen3.c | 67 +++++--
> drivers/media/platform/qcom/camss/camss-vfe.c | 5 +-
> drivers/media/platform/qcom/camss/camss.c | 189 ++++++++++++++++++
> 3 files changed, 242 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen3.c b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
> index 93d16b0951e9..a5eddc8c76ae 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen3
> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen2 (SA8755P/SM8550)
> *
> * Copyright (c) 2024 Qualcomm Technologies, Inc.
> */
> @@ -12,13 +12,41 @@
> #include "camss.h"
> #include "camss-vfe.h"
>
> -#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00)
> +#define IS_VFE_690(vfe) \
> + (vfe->camss->res->version == CAMSS_8775P ? true : false)
> +
Same comment. The "true : false" is a tautology, redundant.
> +#define BUS_REG_BASE_690 \
> + (vfe_is_lite(vfe) ? 0x480 : 0x400)
> +#define BUS_REG_BASE_780 \
> + (vfe_is_lite(vfe) ? 0x200 : 0xC00)
> +#define BUS_REG_BASE \
> + (IS_VFE_690(vfe) ? BUS_REG_BASE_690 : BUS_REG_BASE_780)
> +
> +#define VFE_TOP_CORE_CFG (0x24)
> +
> +#define VFE_BUS_WM_TEST_BUS_CTRL_690 (BUS_REG_BASE + 0xFC)
> +#define VFE_BUS_WM_TEST_BUS_CTRL_780 (BUS_REG_BASE + 0xDC)
> +#define VFE_BUS_WM_TEST_BUS_CTRL \
> + (IS_VFE_690(vfe) ? VFE_BUS_WM_TEST_BUS_CTRL_690 \
> + : VFE_BUS_WM_TEST_BUS_CTRL_780)
> +/*
> + * Bus client mapping:
> + *
> + * Full VFE:
> + * VFE_690: 16 = RDI0, 17 = RDI1, 18 = RDI2
> + * VFE_780: 23 = RDI0, 24 = RDI1, 25 = RDI2
> + *
> + * VFE LITE:
> + * VFE_690 : 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4, 5 = RDI5
> + * VFE_780 : 0 = RDI0, 1 = RDI1, 2 = RDI2, 3 = RDI3, 4 = RDI4
> + */
> +#define RDI_WM_690(n) ((vfe_is_lite(vfe) ? 0x0 : 0x10) + (n))
> +#define RDI_WM_780(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
> +#define RDI_WM(n) (IS_VFE_690(vfe) ? RDI_WM_690(n) : RDI_WM_780(n))
>
> #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
> #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
>
> -#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC)
> -
> #define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100)
> #define WM_CFG_EN BIT(0)
> #define WM_VIR_FRM_EN BIT(1)
> @@ -39,17 +67,6 @@
> #define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100)
> #define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100)
>
> -/*
> - * Bus client mapping:
> - *
> - * Full VFE:
> - * 23 = RDI0, 24 = RDI1, 25 = RDI2
> - *
> - * VFE LITE:
> - * 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4
> - */
> -#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
> -
> static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
> {
> struct v4l2_pix_format_mplane *pix =
> @@ -62,14 +79,23 @@ static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
>
> writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
>
> - writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
> - vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
> + if (IS_VFE_690(vfe))
> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height,
> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
> + else
> + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8,
> + vfe->base + VFE_BUS_WM_FRAME_INCR(wm));
> +
> writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF),
> vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm));
> writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE,
> vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm));
> writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
>
> + /* TOP CORE CFG */
> + if (IS_VFE_690(vfe))
> + writel(0x600000, vfe->base + VFE_TOP_CORE_CFG);
#define BIT(22) SOME_THING
#define BIT(21) SOME_OTHER_THING
writel(SOME_THING | SOME_OTHER_THING, ...);
Its only two bits so please document.
> +
> /* no dropped frames, one irq per frame */
> writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm));
> writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm));
> @@ -92,7 +118,12 @@ static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
> struct vfe_line *line)
> {
> wm = RDI_WM(wm);
> - writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
> +
> + if (IS_VFE_690(vfe))
> + writel(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
> + else
> + writel((addr >> 8) & 0xFFFFFFFF, vfe->base +
> + VFE_BUS_WM_IMAGE_ADDR(wm));
No need to define the bits here 0xFFFFFFFF is obvious.
>
> dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n",
> wm, addr);
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 4bca6c3abaff..99cbe09343f2 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> case CAMSS_8280XP:
> case CAMSS_845:
> case CAMSS_8550:
> + case CAMSS_8775P:
> case CAMSS_X1E80100:
> switch (sink_code) {
> case MEDIA_BUS_FMT_YUYV8_1X16:
> @@ -910,7 +911,8 @@ static int vfe_match_clock_names(struct vfe_device *vfe,
>
> return (!strcmp(clock->name, vfe_name) ||
> !strcmp(clock->name, vfe_lite_name) ||
> - !strcmp(clock->name, "vfe_lite"));
> + !strcmp(clock->name, "vfe_lite") ||
> + !strcmp(clock->name, "camnoc_axi"));
> }
>
> /*
> @@ -1974,6 +1976,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
> case CAMSS_8280XP:
> case CAMSS_845:
> case CAMSS_8550:
> + case CAMSS_8775P:
> case CAMSS_X1E80100:
> ret = 16;
> break;
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index b2398196b9ff..3a11c0a98eb1 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2709,6 +2709,195 @@ static const struct camss_subdev_resources csid_res_8775p[] = {
> },
> };
>
> +static const struct camss_subdev_resources vfe_res_8775p[] = {
> + /* VFE0 */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe0", "vfe0", "vfe0_fast_ahb",
> + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf",
> + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi",
> + "icp_ahb"},
Five AHB clocks - plus three separate AXI clocks ?
I'm not against this list but, please take the time to pick through this
and decide if all of these are really necessary for your SoC.
> + .clock_rate = {
> + { 0 },
> + { 480000000 },
> + { 300000000, 400000000 },
> + { 300000000, 400000000 },
> + { 0 },
> + { 0 },
> + { 0, 80000000 },
> + { 300000000, 400000000 },
> + { 400000000 },
> + { 0 },
> + },
> +
> + .reg = { "vfe0" },
> + .interrupt = { "vfe0" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .has_pd = false,
> + .pd_name = NULL,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE1 */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe1", "vfe1", "vfe1_fast_ahb",
> + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf",
> + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi",
> + "icp_ahb"},
> + .clock_rate = {
> + { 0 },
> + { 480000000 },
> + { 300000000, 400000000 },
> + { 300000000, 400000000 },
> + { 0 },
> + { 0 },
> + { 0, 80000000 },
> + { 300000000, 400000000 },
> + { 400000000 },
> + { 0 },
> + },
> +
> + .reg = { "vfe1" },
> + .interrupt = { "vfe1" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .has_pd = false,
> + .pd_name = NULL,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE2 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 0, 0 },
> + { 300000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 480000000, 600000000, 600000000, 600000000 },
> + },
> + .reg = { "vfe_lite0" },
> + .interrupt = { "vfe_lite0" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE3 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 0, 0 },
> + { 300000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 480000000, 600000000, 600000000, 600000000 },
> + },
> + .reg = { "vfe_lite1" },
> + .interrupt = { "vfe_lite1" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE4 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 0, 0 },
> + { 300000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 480000000, 600000000, 600000000, 600000000 },
> + },
> + .reg = { "vfe_lite2" },
> + .interrupt = { "vfe_lite2" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE5 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 0, 0 },
> + { 300000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 480000000, 600000000, 600000000, 600000000 },
> + },
> + .reg = { "vfe_lite3" },
> + .interrupt = { "vfe_lite3" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE6 (lite) */
> + {
> + .regulators = {},
> +
> + .clock = { "cpas_vfe_lite", "vfe_lite_ahb",
> + "vfe_lite_csid", "vfe_lite_cphy_rx",
> + "vfe_lite"},
> + .clock_rate = {
> + { 0, 0, 0, 0 },
> + { 300000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 400000000, 400000000, 400000000, 400000000 },
> + { 480000000, 600000000, 600000000, 600000000 },
> + },
> + .reg = { "vfe_lite4" },
> + .interrupt = { "vfe_lite4" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .hw_ops = &vfe_ops_gen3,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> +};
> +
> static const struct resources_icc icc_res_sa8775p[] = {
> {
> .name = "ahb",
---bod
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690
2025-07-03 17:19 ` [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690 Vikram Sharma
2025-07-28 14:10 ` Bryan O'Donoghue
@ 2025-09-01 9:04 ` Bryan O'Donoghue
2025-09-01 9:56 ` Vikram Sharma
1 sibling, 1 reply; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-09-01 9:04 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 03/07/2025 18:19, Vikram Sharma wrote:
> + !strcmp(clock->name, "camnoc_axi"));
This is causing a regression on other platforms because they define
camnnoc_axi but not @ the rate of the pixel clock.
In fact its not very obvious why the CAMNOC AXI would want to have a
pixel clock applied to the interconnect fabric.
The following resolves the regression for me. I can either merge with
this change or I'll have to drop the VFE690 changes until you come back
with something else.
➜ deckard@sagittarius-a ~/Development/qualcomm/qlt-kernel
git:(aaa8b5ab704f3) ✗ git diff
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c
b/drivers/media/platform/qcom/camss/camss-vfe.c
index e969de74818f1..1aa0ba5ad8d60 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -913,8 +913,7 @@ static int vfe_match_clock_names(struct vfe_device *vfe,
return (!strcmp(clock->name, vfe_name) ||
!strcmp(clock->name, vfe_lite_name) ||
- !strcmp(clock->name, "vfe_lite") ||
- !strcmp(clock->name, "camnoc_axi"));
+ !strcmp(clock->name, "vfe_lite"));
---
bod
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690
2025-09-01 9:04 ` Bryan O'Donoghue
@ 2025-09-01 9:56 ` Vikram Sharma
0 siblings, 0 replies; 22+ messages in thread
From: Vikram Sharma @ 2025-09-01 9:56 UTC (permalink / raw)
To: Bryan O'Donoghue, rfoss, todor.too, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 9/1/2025 2:34 PM, Bryan O'Donoghue wrote:
> On 03/07/2025 18:19, Vikram Sharma wrote:
>> + !strcmp(clock->name, "camnoc_axi"));
>
> This is causing a regression on other platforms because they define
> camnnoc_axi but not @ the rate of the pixel clock.
>
> In fact its not very obvious why the CAMNOC AXI would want to have a
> pixel clock applied to the interconnect fabric.
>
> The following resolves the regression for me. I can either merge with
> this change or I'll have to drop the VFE690 changes until you come
> back with something else.
Hi Bryan,
updating camnoc axi to 400Mhz was required for TPG test case.
As of now you can Merge VFE patch with below change.
Meanwhile I will work on an alternative approach to set camnoc_axi and
submit as a separate patch.
>
> ➜ deckard@sagittarius-a ~/Development/qualcomm/qlt-kernel
> git:(aaa8b5ab704f3) ✗ git diff
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c
> b/drivers/media/platform/qcom/camss/camss-vfe.c
> index e969de74818f1..1aa0ba5ad8d60 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -913,8 +913,7 @@ static int vfe_match_clock_names(struct vfe_device
> *vfe,
>
> return (!strcmp(clock->name, vfe_name) ||
> !strcmp(clock->name, vfe_lite_name) ||
> - !strcmp(clock->name, "vfe_lite") ||
> - !strcmp(clock->name, "camnoc_axi"));
> + !strcmp(clock->name, "vfe_lite"));
>
> ---
> bod
Best regards,
Vikram
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 9/9] media: qcom: camss: Enumerate resources for SA8775P
2025-07-03 17:19 [PATCH v3 0/9] Add sa8775p camss support Vikram Sharma
` (7 preceding siblings ...)
2025-07-03 17:19 ` [PATCH v3 8/9] media: qcom: camss: Add support for VFE 690 Vikram Sharma
@ 2025-07-03 17:19 ` Vikram Sharma
2025-07-28 14:10 ` Bryan O'Donoghue
8 siblings, 1 reply; 22+ messages in thread
From: Vikram Sharma @ 2025-07-03 17:19 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, andersson, konradybcio, hverkuil-cisco,
cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, quic_svankada, linux-media,
linux-arm-msm, devicetree, linux-kernel
Enumerate csiphy, csid and vfe resources for SA8775P.
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
---
drivers/media/platform/qcom/camss/camss.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 3a11c0a98eb1..b6e80088d1df 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -4185,7 +4185,14 @@ static const struct camss_resources msm8996_resources = {
static const struct camss_resources sa8775p_resources = {
.version = CAMSS_8775P,
.pd_name = "top",
+ .csiphy_res = csiphy_res_8775p,
+ .csid_res = csid_res_8775p,
+ .csid_wrapper_res = &csid_wrapper_res_sa8775p,
+ .vfe_res = vfe_res_8775p,
.icc_res = icc_res_sa8775p,
+ .csiphy_num = ARRAY_SIZE(csiphy_res_8775p),
+ .csid_num = ARRAY_SIZE(csid_res_8775p),
+ .vfe_num = ARRAY_SIZE(vfe_res_8775p),
.icc_path_num = ARRAY_SIZE(icc_res_sa8775p),
.link_entities = camss_link_entities
};
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 9/9] media: qcom: camss: Enumerate resources for SA8775P
2025-07-03 17:19 ` [PATCH v3 9/9] media: qcom: camss: Enumerate resources for SA8775P Vikram Sharma
@ 2025-07-28 14:10 ` Bryan O'Donoghue
0 siblings, 0 replies; 22+ messages in thread
From: Bryan O'Donoghue @ 2025-07-28 14:10 UTC (permalink / raw)
To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt,
andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers,
catalin.marinas, will
Cc: linux-arm-kernel, quic_svankada, linux-media, linux-arm-msm,
devicetree, linux-kernel
On 03/07/2025 18:19, Vikram Sharma wrote:
> Enumerate csiphy, csid and vfe resources for SA8775P.
>
> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
> ---
> drivers/media/platform/qcom/camss/camss.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 3a11c0a98eb1..b6e80088d1df 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -4185,7 +4185,14 @@ static const struct camss_resources msm8996_resources = {
> static const struct camss_resources sa8775p_resources = {
> .version = CAMSS_8775P,
> .pd_name = "top",
> + .csiphy_res = csiphy_res_8775p,
> + .csid_res = csid_res_8775p,
> + .csid_wrapper_res = &csid_wrapper_res_sa8775p,
> + .vfe_res = vfe_res_8775p,
> .icc_res = icc_res_sa8775p,
> + .csiphy_num = ARRAY_SIZE(csiphy_res_8775p),
> + .csid_num = ARRAY_SIZE(csid_res_8775p),
> + .vfe_num = ARRAY_SIZE(vfe_res_8775p),
> .icc_path_num = ARRAY_SIZE(icc_res_sa8775p),
> .link_entities = camss_link_entities
> };
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 22+ messages in thread