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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6760fbbbasm765535266b.146.2025.01.28.03.20.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jan 2025 03:20:45 -0800 (PST) Message-ID: <3cb2c5d6-3ee2-4a48-96c2-40f464c22f52@oss.qualcomm.com> Date: Tue, 28 Jan 2025 12:20:42 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 4/4] PCI: dwc: Add support for configuring lane equalization presets To: Krishna Chaitanya Chundru , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio References: <20250128-preset_v2-v5-0-4d230d956f8c@oss.qualcomm.com> <20250128-preset_v2-v5-4-4d230d956f8c@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250128-preset_v2-v5-4-4d230d956f8c@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: luTzS0vzggD51jYn9v3Fmz9oMQ4R-l8d X-Proofpoint-ORIG-GUID: luTzS0vzggD51jYn9v3Fmz9oMQ4R-l8d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-28_04,2025-01-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501280087 On 28.01.2025 10:37 AM, Krishna Chaitanya Chundru wrote: > PCIe equalization presets are predefined settings used to optimize > signal integrity by compensating for signal loss and distortion in > high-speed data transmission. > > Based upon the number of lanes and the data rate supported, write > the preset data read from the device tree in to the lane equalization > control registers. > > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 41 +++++++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 3 ++ > include/uapi/linux/pci_regs.h | 3 ++ > 3 files changed, 47 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 2cd0acbf9e18..f458b4c70053 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > if (pci->num_lanes < 1) > pci->num_lanes = dw_pcie_link_get_max_link_width(pci); > > + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); > + if (ret) > + goto err_free_msi; > + > /* > * Allocate the resource for MSG TLP before programming the iATU > * outbound window in dw_pcie_setup_rc(). Since the allocation depends > @@ -802,6 +806,42 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > return 0; > } > > +static void dw_pcie_program_presets(struct dw_pcie *pci, u8 cap_id, u8 lane_eq_offset, > + u8 lane_reg_size, u8 *presets, u8 num_lanes) > +{ > + u32 cap; > + int i; > + > + cap = dw_pcie_find_ext_capability(pci, cap_id); > + if (!cap) > + return; > + > + /* > + * Write preset values to the registers byte-by-byte for the given > + * number of lanes and register size. > + */ > + for (i = 0; i < num_lanes * lane_reg_size; i++) > + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); > +} > + > +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed]; > + > + /* For data rate of 8 GT/S each lane equalization control is 16bits wide */ > + if (speed >= PCIE_SPEED_8_0GT && pp->presets.eq_presets_8gts[0] != PCI_EQ_RESV) > + dw_pcie_program_presets(pci, PCI_EXT_CAP_ID_SECPCI, PCI_SECPCI_LE_CTRL, > + 0x2, (u8 *)pp->presets.eq_presets_8gts, pci->num_lanes); If you move the != RESERVED into dw_pcie_program_presets, this becomes more readable otherwise, this looks good Konrad