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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22dc5aaaa54sm2693295ad.227.2025.04.25.09.10.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Apr 2025 09:11:00 -0700 (PDT) Message-ID: <3ceda07a-7261-48c4-aa60-fd5ad83ebf34@oss.qualcomm.com> Date: Fri, 25 Apr 2025 10:10:58 -0600 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] bus: mhi: host: Allocate entire MHI control config once To: Manivannan Sadhasivam Cc: quic_carlv@quicinc.com, quic_thanson@quicinc.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, Pranjal Ramajor Asha Kanojiya , ath11k@lists.infradead.org, jjohnson@kernel.org, quic_bqiang@quicinc.com References: <20250328165913.3380933-1-jeff.hugo@oss.qualcomm.com> <07cc4ee2-4a13-495c-bc4d-8837d6b54414@oss.qualcomm.com> Content-Language: en-US From: Jeff Hugo In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: rTkbsTAxC-kKuj0Yo5X0nUumXI5i4KFk X-Authority-Analysis: v=2.4 cv=OY6YDgTY c=1 sm=1 tr=0 ts=680bb417 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=KGs-PxyYlbaIbUy0pvQA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: rTkbsTAxC-kKuj0Yo5X0nUumXI5i4KFk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDExNSBTYWx0ZWRfXwhNwEYNXD/pl zpbi3/I2ibowJdHa+6R79HNPvnRafGwJ36AF6IZeUQQGqtQL4ivSZnspBTs1tfL6pQZhFHHWT81 gHKkYw6NlKcbTAMvWCF8kMNJpgDxwHq96lxEUJYhoWUC3yi/fuoa0jrQtufZw345ULFDsyMbqk6 qKfO1WQd2ZxjfvyM81KnpS49UQ82m6HbtopepA3BeInAtkkwHdb2QLuXLcNcwoIRK9UX4psb9sQ 9P5AjQaN6+HvAcQV7SCDnblQFuHeEIsz1RZ3t5xUVy4ZGjajosMmlESzE4t3TDbwgU4s1qmHgDZ qvMWjUqafP28xwA7nbX9LESqaIYzOKR1fzFHB0nMZtVd2lD1FQhitq3KL2dpZpv4KUn0lPR/NQu 4mHaAK9S3S/2vEjVnj6Q+VZHmGjKneEM/4SzvF+3gMscikYn8D1RcOZX4KfoKmUmxSUczqOC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_04,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250115 On 4/24/2025 11:37 PM, Manivannan Sadhasivam wrote: > + ath11k list, Jeff and Baochen (for question regarding the use of reserved > memory for allocating the MHI data structures in host) > > On Tue, Apr 08, 2025 at 08:56:43AM -0600, Jeff Hugo wrote: >> On 4/8/2025 1:01 AM, Manivannan Sadhasivam wrote: >>> On Fri, Mar 28, 2025 at 10:59:13AM -0600, Jeff Hugo wrote: >>>> From: Pranjal Ramajor Asha Kanojiya >>>> >>>> MHI control configurations such as channel context, event context, command >>>> context and rings, are currently allocated individually. During MHI >>>> initialization MHI bus driver needs to configure the address space in >>>> which this control configuration resides. Since different component of the >>>> config is being allocated separately, only logical solution is to give the >>>> entire RAM address space, as they could be anywhere. >>>> >>> >>> This is fine... >> >> We tripped over this when experimenting with an automotive market product. >> The FW for that product had a rather strict interpretation of the spec, >> which we confirmed with the spec owner. >> >> In the specific FW implementation, the device maps the entire MHI space of >> shared structures in a single ATU entry. The device cannot map an entire >> 64-bit address space, and it expects all of the shared structures in a >> single compact range. >> >> This applies to the control structures, not the data buffers per the device >> implementation. >> >> This restriction seems backed by the spec. I can't find a reason why the >> device is invalid, if limited. I don't think this should break anything, >> but more on that below. >> > > Yes, atleast I have heard about that limitation before. > >>> >>>> As per MHI specification the MHI control configuration address space should >>>> not be more them 4GB. >>>> >>> >>> Where exactly this limitation is specified in the spec? The spec supports full >>> 64 bit address space for the MHI control/data structures. But due to the device >>> DMA limitations, MHI controller drivers often use 32 bit address space. But >>> that's not a spec limitation. >> >> Its not the clearest thing, sadly. >> >> Document 80-NF223-11 Rev AB "MHI spec v1.2" Section 6.2 "MHI Registers" >> table 6-19 (page 106) - >> >> Describing MHICTRLLIMIT: "The most significant 32 bits of MHICTRLBASE and >> MHICTRLLIMIT registers must be equal." >> >> This means we have a 4GB range (32-bit) to play with in a 64-bit address >> space. If the upper 32-bits of the 64-bit address for both the base and the >> limit must be the same, then the range of addresses from the base to the >> limit can only vary the lower 32-bits. >> >> Invalid: >> BASE: 0x0 >> LIMIT: 0xffffffff_ffffffff >> >> Valid: >> BASE: 0x0f_00000000 >> LIMIT: 0x0f_ffffffff >> > > Ah. Didn't spot this before, thanks for explaining! > >>>> Since the current implementation is in violation of MHI specification. >> >> For example mhi_init_dev_ctxt() >> >> We allocate the chan_ctxt with dma_alloc_coherent() as an individual >> allocation. In the case of AIC100, the device can access the full 64-bit >> address space, but the DMA engine is limited to a 32-bit transfer size. The >> chan_ctxt probably won't be larger than 4GB, so the size is rather >> irrelevant. Can be allocated anywhere. Lets say that it gets put in the >> lower 32-bit address space - 0x0_XXXXXXXX >> >> Then a little bit later we allocate er_ctxt with a different >> dma_alloc_coherent() instance. Being a unique allocation, it is not tied to >> the chan_ctxt and can exist anywhere. Lets assume that it gets put >> somewhere in the non-lower 32-bits - 0x1000_XXXXXXXX >> >> Now we have a problem because we cannot describe a single range covering >> both of these allocations via MHICTRLBASE/MHICTRLLIMIT where the upper >> 32-bits of both registers is the same. >> > > Yes, I get it. I do not have issues in allocating all the structures in one go. > But the problem is with MHICTRL_BASE/LIMIT. More below. > >>>> Allocate a single giant DMA buffer for MHI control configurations and >>>> limit the configuration address space to that buffer. >>>> >>> >>> I don't think this could work for all devices. For instance, some ath11k devices >>> use a fixed reserved region in host address space for MHICTRL/BASE. >> >> Why would we be unable to allocate all of the control structures in a single >> allocation out of that reserved region? Is it larger than 4GB in size? >> > > I was confused by the fact that ath11k driver adds an offset of 0x1000000 to the > reserved region for the iova_start: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/wireless/ath/ath11k/mhi.c?h=v6.15-rc3#n331 > > So this means the firmware will only map the memory from reserved + 0x1000000 > for MHI data structures. But even with current implementation, the MHI stack > doesn't know anything about the offset, because it just relies on > dma_alloc_coherent() API which will only honor the reserved region pointed by > 'memory' property in the node (without the offset). > > So I'm not sure how the firmware makes sure that the data structures lives > within the offset region. This is more of a question to ath11k folks. > > But your series is not going to make it any worse. Sorry about the confusion. No problem. I appreciate the sanity check. -Jeff