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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63788111f1fsm14431758a12.36.2025.10.08.01.26.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Oct 2025 01:26:04 -0700 (PDT) Message-ID: <3f1979d4-1438-4c9d-99db-d97a09c5c35b@oss.qualcomm.com> Date: Wed, 8 Oct 2025 10:26:02 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/8] media: iris: enable support for SC7280 platform To: Dmitry Baryshkov , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251008-iris-sc7280-v1-0-def050ba5e1f@oss.qualcomm.com> <20251008-iris-sc7280-v1-8-def050ba5e1f@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251008-iris-sc7280-v1-8-def050ba5e1f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA0MDAwMSBTYWx0ZWRfXyvuw8yWa1+zB 1YbMxc6agTzpj5H3zrOK5EHc1xcMYZFa3i4y41LVCoFF38v9GWQod8HkoGlcgqnDJENst8moRKI 2S8yvm5nZ+9CeHaK9R2s78PveeZVrIJjVa6ePUmOI3kNCwt4MtnosXTYSpnXRzIwjspDH1iucmm g9a8f9xesNXsW0eU9e3lLUVY2J5lx3Xjr35qxz5YA+2fGucvWLyM7Vg2eekeMAAfqEDULb3abMY sInO4nnLJVFA4KSl/cKrf5S4xd5uDhrte6pgliDZRRiJkF9vmHoacNPS3YRmdAiuGsIWxPGjecI qEDy36g8sRc8O2vakdRb2XRAHneF2rcyXCQO1A4Fg9ON1IJScgvL8wC+bdBqq7kOkx8ZdPkocz4 x/OflgoHTC0aKMq4xhW3nVEDtcoAMg== X-Proofpoint-GUID: EMIKeXuaQr6ebbO-q-GkJx3xAN0703_U X-Proofpoint-ORIG-GUID: EMIKeXuaQr6ebbO-q-GkJx3xAN0703_U X-Authority-Analysis: v=2.4 cv=EqnfbCcA c=1 sm=1 tr=0 ts=68e6201e cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=j50RDpsK6yXKt_5VL_0A:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-08_01,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2510040001 On 10/8/25 6:33 AM, Dmitry Baryshkov wrote: > As a part of migrating code from the old Venus driver to the new Iris > one, add support for the SC7280 platform. It is very similar to SM8250, > but it (currently) uses no reset controls (there is an optional > GCC-generated reset, it will be added later) and no AON registers > region. The Venus driver names this platform "IRIS2_1", so the ops in Which we've learnt in the past is "IRIS2, 1-pipe" > the driver are also now called iris_vpu21_ops. > > Signed-off-by: Dmitry Baryshkov > --- > .../platform/qcom/iris/iris_platform_common.h | 3 + > .../media/platform/qcom/iris/iris_platform_gen1.c | 66 +++++++++++ > drivers/media/platform/qcom/iris/iris_probe.c | 4 + > drivers/media/platform/qcom/iris/iris_vpu2.c | 130 +++++++++++++++++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + > 5 files changed, 204 insertions(+) > > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h > index 104ff38219e30e6d52476d44b54338c55ef2ca7b..36e33eb05a6918de590feca37b41c07a92e9c434 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h > @@ -42,6 +42,7 @@ enum pipe_type { > }; > > extern const struct iris_platform_data qcs8300_data; > +extern const struct iris_platform_data sc7280_data; > extern const struct iris_platform_data sm8250_data; > extern const struct iris_platform_data sm8550_data; > extern const struct iris_platform_data sm8650_data; > @@ -50,7 +51,9 @@ extern const struct iris_platform_data sm8750_data; > enum platform_clk_type { > IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ > IRIS_CTRL_CLK, > + IRIS_AHB_CLK, Interestingly, 8250 also has an AHB clock, but the clock driver keeps it always-on.. > IRIS_HW_CLK, > + IRIS_HW_AXI_CLK, This exists on SC7280 and SM6350, perhaps as a result of the bus topology > IRIS_AXI1_CLK, > IRIS_CTRL_FREERUN_CLK, > IRIS_HW_FREERUN_CLK, > diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c > index 2b3b8bd00a6096acaae928318d9231847ec89855..d5288a71a6a8289e5ecf69b6f38231500f2bf8b4 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c > +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c > @@ -364,3 +364,69 @@ const struct iris_platform_data sm8250_data = { > .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl, > .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), > }; > + > +static const struct bw_info sc7280_bw_table_dec[] = { > + { ((3840 * 2160) / 256) * 60, 1896000, }, > + { ((3840 * 2160) / 256) * 30, 968000, }, > + { ((1920 * 1080) / 256) * 60, 618000, }, > + { ((1920 * 1080) / 256) * 30, 318000, }, > +}; > + > +static const char * const sc7280_opp_pd_table[] = { "cx" }; Wonder why this is different.. Oh, I can bet good money SM8250's Venus isn't fed off of MX alone.. Let's check the sauce.. It was always supposed to be M*MC*X with MX just for the VIDEO_CC PLLs.. [...] > +/* > + * This is the same as iris_vpu_power_off_controller except > + * AON_WRAPPER_MVP_NOC_LPI_CONTROL / AON_WRAPPER_MVP_NOC_LPI_STATUS programming > + * and with added IRIS_AHB_CLK handling > + */ > +static int iris_vpu21_power_off_controller(struct iris_core *core) This is 1 : 1 the existing sm8250 code except...> +{ > + u32 val = 0; > + int ret; > + > + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH); > + > + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL); > + > + ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS, > + val, val & BIT(0), 200, 2000); > + if (ret) > + goto disable_power; > + > + writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); > + > + ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS, > + val, val == 0, 200, 2000); > + if (ret) > + goto disable_power; > + > + writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, > + core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); > + writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); > + writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); > + writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); > + > +disable_power: > + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); ..for this line but this could be added to that one instead, since both clk APIs and the Iris wrappers around it are happy to consume a null pointer (funnily enough this one returns !void and is never checked) similar story for other func additions Konrad