From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE31127FB37; Wed, 18 Jun 2025 09:08:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750237699; cv=none; b=ZYqnzivDd4HH58ECvZ7ypO50kpmlXtDHhv80ujmA6KFKG+rjJ2mk63Hf8e7Zztmwqz6T53aw9voBRXJfo4ACHOVv7MtDoPpuikA3SlKPBZT2eMBOu/WEutA/1fNQwwoKsdIRgCKFGhg2j8epFDcBy58/v7ixdOh/mmiPaunWHws= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750237699; c=relaxed/simple; bh=Znwom1NdED/dYAH4xL7nUXQjN8SthFU/dT6KAA1gfL8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=f4lXkkAIrpsIL9pX02vVH0D6huSrv8NhZXpw9oMUz/zRwmLYj/RFc/AGQG5iAwEAhekDDDNGtC/FULTUJgU4XyOVjbZXqV3p517HsU94Qu7i9FXI6MimxD6mlAl4p5ydO/6lKPcRXbB119gV3UGjArkAqAAJ+WVvgA3zdHIE4tM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rahVlYsM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rahVlYsM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0702FC4CEE7; Wed, 18 Jun 2025 09:08:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750237696; bh=Znwom1NdED/dYAH4xL7nUXQjN8SthFU/dT6KAA1gfL8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=rahVlYsMunMFBAizbh5HnPv5AZIpKAQgZnJ/W0DL/VlmB5Gtf9xlpNPARl95XPdTo XH4Y3zjaeSgIn/orTF4ZbT4nq36/rmwPhoZrc1EaORsjvCDQmssdi3+zdqWt9Ay4Py ABO+/r2KE7ZxL6HgzpBcJuBuf2spYrE4tEhrh0dv+f3n86OfMR6+nlwumzy4iRQMRS 6H4co0s+c0SYlI1EaoWWAy0NGHnAsVLMiIhEGIC6OGxf7Od0u8ytMxmMpQOZ0ndEil Pc1EskmmzpDlwQtT04GoWkJ3QiCEbMa8le6RGMicaf8TIcHudq+qucyYFvuuEAhT3l X4lrskt3+JI8g== Message-ID: <4038339c-a352-4007-85f5-44601a3578c2@kernel.org> Date: Wed, 18 Jun 2025 11:08:10 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 4/4] arm64: dts: qcom: sm8550: Remove SDR104/SDR50 broken capabilities To: Sarthak Garg , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20250618072818.1667097-1-quic_sartgarg@quicinc.com> <20250618072818.1667097-5-quic_sartgarg@quicinc.com> <5336c00d-3b80-423a-bb52-4e1ec35bc7ed@kernel.org> <86ad5ddb-1a43-45c3-af35-9eb863c66f63@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 18/06/2025 10:44, Sarthak Garg wrote: > > > On 6/18/2025 1:11 PM, Krzysztof Kozlowski wrote: >> On 18/06/2025 09:28, Sarthak Garg wrote: >>> Kernel now handles all level shifter limitations related to SD card >>> modes. >>> As a result, the broken hardware capabilities for SDR104 and SDR50 modes >>> can be removed from the device tree. >>> Additionally, due to level shifter constraints, set the maximum >>> frequency for High Speed (HS) mode to 37.5 MHz using the >>> max-sd-hs-frequency property for sm8550. >>> >>> Signed-off-by: Sarthak Garg >>> --- >>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 +--- >>> 1 file changed, 1 insertion(+), 3 deletions(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>> index 82cabf777cd2..2c770c979d39 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>> @@ -3180,6 +3180,7 @@ sdhc_2: mmc@8804000 { >>> iommus = <&apps_smmu 0x540 0>; >>> qcom,dll-config = <0x0007642c>; >>> qcom,ddr-config = <0x80040868>; >>> + max-sd-hs-frequency = <37500000>; >> So my previous comments stay... This is SoC thus deducible from compatible. >> >> Best regards, >> Krzysztof > > " I agree that a DT property for the mmc controller would make sense. > > Although, this seems limited to SD UHS-I speed modes, so perhaps > "max-sd-uhs-frequency" would be a better name for it? > > Kind regards > Uffe " > > https://patchwork.kernel.org/project/linux-mmc/cover/20250523105745.6210-1-quic_sartgarg@quicinc.com/ > > This was the comment given on V2 to introduce a generic dt > property. I know, it does not matter. If this is here, it is a 100% proof this is SoC specific, thus you have compatible for that. Best regards, Krzysztof