[PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

[PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Define ports {} for the DWC controller & the QMPPHY and connect them
together for the SS lanes.

Leave the DP endpoint unconnected for now, as both Aspire 1 and the
Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
Take the creative liberty to add a newline before its ports' subnodes
though.

[1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/

Suggested-by: Rob Herring (Arm) <robh@kernel.org>
Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 8f827f1d8515d6113c85a2ecacf7ac364e195242..a0df10a97c7f8aa5cd468c8983e74256490d1d06 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2897,6 +2897,31 @@ usb_1_qmpphy: phy@88e8000 {
 
 			#clock-cells = <1>;
 			#phy-cells = <1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_1_qmpphy_out: endpoint { };
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_1_qmpphy_usb_ss_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usb_1_qmpphy_dp_in: endpoint { };
+				};
+			};
 		};
 
 		pmu@90b6300 {
@@ -3070,6 +3095,26 @@ usb_1_dwc3: usb@a600000 {
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				maximum-speed = "super-speed";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						usb_1_dwc3_hs: endpoint {
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						usb_1_dwc3_ss: endpoint {
+							remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+						};
+					};
+				};
 			};
 		};
 
@@ -3384,8 +3429,10 @@ mdss_dp: displayport-controller@ae90000 {
 				ports {
 					#address-cells = <1>;
 					#size-cells = <0>;
+
 					port@0 {
 						reg = <0>;
+
 						dp_in: endpoint {
 							remote-endpoint = <&dpu_intf0_out>;
 						};
@@ -3393,6 +3440,7 @@ dp_in: endpoint {
 
 					port@1 {
 						reg = <1>;
+
 						mdss_dp_out: endpoint { };
 					};
 				};

---
base-commit: b1549501188cc9eba732c25b033df7a53ccc341f
change-id: 20250808-topic-7180_qmpphy_ports-e63404331685

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

[Dmitry Baryshkov]

On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Define ports {} for the DWC controller & the QMPPHY and connect them
> together for the SS lanes.
> 
> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.

If I remember correctly, on SC7180 the DP is still routed through USB+DP
combo PHY rather than having a separate output. I'd let Nikita to
comment though.

For the patch:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


> Take the creative liberty to add a newline before its ports' subnodes
> though.
> 
> [1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/
> 
> Suggested-by: Rob Herring (Arm) <robh@kernel.org>
> Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 

-- 
With best wishes
Dmitry

Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

[Nikita Travkin]

Dmitry Baryshkov писал(а) 09.08.2025 12:49:
> On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> 
>> Define ports {} for the DWC controller & the QMPPHY and connect them
>> together for the SS lanes.
>> 
>> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
>> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
> 
> If I remember correctly, on SC7180 the DP is still routed through USB+DP
> combo PHY rather than having a separate output. I'd let Nikita to
> comment though.

Per my understanding SC7180 has only one DP connected via SS+DP combophy
(At least this is the only thing that is exposed by the QSIP module)

On Aspire 1 the SoC USB0 is hard-wired like so:

  sc7180        USB3 Hub             Type-C DP Switch
--------+     +---------------+    +-----------------+
 SS_TX0 | --> | SS_TX   P1_TX | -> | SS Tx           |
 SS_RX0 | --> | SS_RX   P1_RX | -> | SS Rx     Out   |
        |     +---------------+    |        (4lanes) | ==> [Type-C]
        |                          |                 |
 SS_TX1 | -----------------------> | DP Mux ML1      |
 SS_RX1 | -----------------------> | DP Mux ML0      |
--------+                          +-----------------+

So, basically, the SoC combphy is assumed to do 2+2 DP alt mode in
primary orientation, and the actual orientation switching is done
by a separate DP mux/switch (Represented under EC in Aspire 1, there are
multiple chips roughly governed by EC that make it tick)

Currently this is represented by merely connecting the MDSS DP to
the EC node directly (to represent the link between TX/RX1 and Switch)
where the EC node implements a bridge injecting the HPD signal, which
I assume worked out because the combphy driver so far just hardocded
the correct 2+2 config by default.

However if we want to rope in combphy into this (which I guess we want
to actually configure combphy and not assume it works), we'd want to
connect mdss to combphy and combphy to EC at least in Aspire 1 case.


Nikita


> 
> For the patch:
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> 
> 
>> Take the creative liberty to add a newline before its ports' subnodes
>> though.
>> 
>> [1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/
>> 
>> Suggested-by: Rob Herring (Arm) <robh@kernel.org>
>> Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 48 insertions(+)
>>

Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

[Dmitry Baryshkov]

On Sat, Aug 09, 2025 at 02:43:47PM +0500, Nikita Travkin wrote:
> Dmitry Baryshkov писал(а) 09.08.2025 12:49:
> > On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
> >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >> 
> >> Define ports {} for the DWC controller & the QMPPHY and connect them
> >> together for the SS lanes.
> >> 
> >> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
> >> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
> > 
> > If I remember correctly, on SC7180 the DP is still routed through USB+DP
> > combo PHY rather than having a separate output. I'd let Nikita to
> > comment though.
> 
> Per my understanding SC7180 has only one DP connected via SS+DP combophy
> (At least this is the only thing that is exposed by the QSIP module)
> 
> On Aspire 1 the SoC USB0 is hard-wired like so:
> 
>   sc7180        USB3 Hub             Type-C DP Switch
> --------+     +---------------+    +-----------------+
>  SS_TX0 | --> | SS_TX   P1_TX | -> | SS Tx           |
>  SS_RX0 | --> | SS_RX   P1_RX | -> | SS Rx     Out   |
>         |     +---------------+    |        (4lanes) | ==> [Type-C]
>         |                          |                 |
>  SS_TX1 | -----------------------> | DP Mux ML1      |
>  SS_RX1 | -----------------------> | DP Mux ML0      |
> --------+                          +-----------------+
> 
> So, basically, the SoC combphy is assumed to do 2+2 DP alt mode in
> primary orientation, and the actual orientation switching is done
> by a separate DP mux/switch (Represented under EC in Aspire 1, there are
> multiple chips roughly governed by EC that make it tick)
> 
> Currently this is represented by merely connecting the MDSS DP to
> the EC node directly (to represent the link between TX/RX1 and Switch)
> where the EC node implements a bridge injecting the HPD signal, which
> I assume worked out because the combphy driver so far just hardocded
> the correct 2+2 config by default.
> 
> However if we want to rope in combphy into this (which I guess we want
> to actually configure combphy and not assume it works), we'd want to
> connect mdss to combphy and combphy to EC at least in Aspire 1 case.

Yes, please (especially as you have hardware to test). I'd really prefer
to have DP being connected to the combo PHY (as all other platforms do)
and then we can manually /delete-property/ orientation-switch inside
boards's DT (as it is not being used for switching).

We have a way to describe onboard HUB connections (see the second USB-C
connector on C630).

-- 
With best wishes
Dmitry

Re: [PATCH] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths

[Bjorn Andersson]

On Fri, Aug 08, 2025 at 11:20:45AM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Define ports {} for the DWC controller & the QMPPHY and connect them
> together for the SS lanes.

Sounds quite reasonable to me, but I can only guess why you think it's a
good idea. Please start with a paragraph documenting which problem
you're solving.

Regards,
Bjorn

> 
> Leave the DP endpoint unconnected for now, as both Aspire 1 and the
> Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
> Take the creative liberty to add a newline before its ports' subnodes
> though.
> 
> [1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/
> 
> Suggested-by: Rob Herring (Arm) <robh@kernel.org>
> Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 8f827f1d8515d6113c85a2ecacf7ac364e195242..a0df10a97c7f8aa5cd468c8983e74256490d1d06 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -2897,6 +2897,31 @@ usb_1_qmpphy: phy@88e8000 {
>  
>  			#clock-cells = <1>;
>  			#phy-cells = <1>;
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +
> +					usb_1_qmpphy_out: endpoint { };
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					usb_1_qmpphy_usb_ss_in: endpoint {
> +						remote-endpoint = <&usb_1_dwc3_ss>;
> +					};
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +
> +					usb_1_qmpphy_dp_in: endpoint { };
> +				};
> +			};
>  		};
>  
>  		pmu@90b6300 {
> @@ -3070,6 +3095,26 @@ usb_1_dwc3: usb@a600000 {
>  				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
>  				phy-names = "usb2-phy", "usb3-phy";
>  				maximum-speed = "super-speed";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						usb_1_dwc3_hs: endpoint {
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +
> +						usb_1_dwc3_ss: endpoint {
> +							remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
> +						};
> +					};
> +				};
>  			};
>  		};
>  
> @@ -3384,8 +3429,10 @@ mdss_dp: displayport-controller@ae90000 {
>  				ports {
>  					#address-cells = <1>;
>  					#size-cells = <0>;
> +
>  					port@0 {
>  						reg = <0>;
> +
>  						dp_in: endpoint {
>  							remote-endpoint = <&dpu_intf0_out>;
>  						};
> @@ -3393,6 +3440,7 @@ dp_in: endpoint {
>  
>  					port@1 {
>  						reg = <1>;
> +
>  						mdss_dp_out: endpoint { };
>  					};
>  				};
> 
> ---
> base-commit: b1549501188cc9eba732c25b033df7a53ccc341f
> change-id: 20250808-topic-7180_qmpphy_ports-e63404331685
> 
> Best regards,
> -- 
> Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>