From: James Clark <james.clark@linaro.org>
To: Jie Gan <quic_jiegan@quicinc.com>
Cc: Tingwei Zhang <quic_tingweiz@quicinc.com>,
Jinlong Mao <quic_jinlmao@quicinc.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Subject: Re: [PATCH v9 5/6] Coresight: Add Coresight TMC Control Unit driver
Date: Tue, 28 Jan 2025 11:55:51 +0000 [thread overview]
Message-ID: <44bd0d5e-a232-49c3-ba2f-e63e2f2c99be@linaro.org> (raw)
In-Reply-To: <20250124072537.1801030-6-quic_jiegan@quicinc.com>
On 24/01/2025 7:25 am, Jie Gan wrote:
> The Coresight TMC Control Unit hosts miscellaneous configuration registers
> which control various features related to TMC ETR sink.
>
> Based on the trace ID, which is programmed in the related CTCU ATID
> register of a specific ETR, trace data with that trace ID gets into
> the ETR buffer, while other trace data gets dropped.
>
> Enabling source device sets one bit of the ATID register based on
> source device's trace ID.
> Disabling source device resets the bit according to the source
> device's trace ID.
>
> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
> ---
> drivers/hwtracing/coresight/Kconfig | 12 +
> drivers/hwtracing/coresight/Makefile | 1 +
> drivers/hwtracing/coresight/coresight-ctcu.c | 276 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-ctcu.h | 30 ++
> include/linux/coresight.h | 3 +-
> 5 files changed, 321 insertions(+), 1 deletion(-)
> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.c
> create mode 100644 drivers/hwtracing/coresight/coresight-ctcu.h
>
[...]
> +/*
> + * ctcu_set_etr_traceid: Retrieve the ATID offset and trace ID.
> + *
> + * Returns 0 indicates success. None-zero result means failure.
> + */
> +static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *cs_path,
> + bool enable)
> +{
> + struct coresight_device *sink = coresight_get_sink(cs_path->path);
> + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + u8 trace_id = cs_path->trace_id;
> + int port_num;
> +
> + if ((sink == NULL) || !IS_VALID_CS_TRACE_ID(trace_id) || IS_ERR_OR_NULL(drvdata)) {
> + dev_err(&csdev->dev, "Invalid parameters\n");
> + return -EINVAL;
> + }
> +
> + port_num = ctcu_get_active_port(sink, csdev);
> + if (port_num < 0)
> + return -EINVAL;
> +
> + /*
> + * Skip the disable session if more than one TPDM device that
> + * connected to the same TPDA device has been enabled.
> + */
> + if (enable)
> + atomic_inc(&drvdata->traceid_refcnt[port_num][trace_id]);
> + else {
> + if (atomic_dec_return(&drvdata->traceid_refcnt[port_num][trace_id]) > 0) {
> + dev_dbg(&csdev->dev, "Skip the disable session\n");
> + return 0;
> + }
> + }
> +
> + dev_dbg(&csdev->dev, "traceid is %d\n", cs_path->trace_id);
> +
> + return __ctcu_set_etr_traceid(csdev, trace_id, port_num, enable);
Hi Jie,
Using atomic_dec_return() here doesn't prevent __ctcu_set_etr_traceid()
from running concurrent enable and disables. Once you pass the
atomic_dec_return() a second call to enable it will mess it up.
I think you need a spinlock around the whole thing and then the
refcounts don't need to be atomics.
next prev parent reply other threads:[~2025-01-28 11:55 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-24 7:25 [PATCH v9 0/6] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2025-01-24 7:25 ` [PATCH v9 1/6] Coresight: Add support for new APB clock name Jie Gan
2025-01-24 7:25 ` [PATCH v9 2/6] Coresight: Add trace_id function to retrieving the trace ID Jie Gan
2025-01-24 7:25 ` [PATCH v9 3/6] Coresight: Introduce a new struct coresight_path Jie Gan
2025-01-28 11:54 ` James Clark
2025-01-29 0:57 ` Jie Gan
2025-01-31 16:36 ` [PATCH 0/3] coresight: Alloc trace ID after building the path James Clark
2025-01-31 16:36 ` [PATCH 1/3] coresight: Don't save handle in path James Clark
2025-02-06 3:02 ` Jie Gan
2025-02-06 14:34 ` James Clark
2025-01-31 16:36 ` [PATCH 2/3] coresight: Export coresight_get_sink() James Clark
2025-01-31 16:36 ` [PATCH 3/3] coresight: Alloc trace ID after building the path James Clark
2025-02-05 4:13 ` [PATCH 0/3] " Jie Gan
2025-02-05 7:44 ` Jie Gan
2025-01-31 16:43 ` [PATCH v9 3/6] Coresight: Introduce a new struct coresight_path James Clark
2025-02-05 4:09 ` Jie Gan
2025-01-24 7:25 ` [PATCH v9 4/6] dt-bindings: arm: Add Coresight TMC Control Unit hardware Jie Gan
2025-01-24 7:25 ` [PATCH v9 5/6] Coresight: Add Coresight TMC Control Unit driver Jie Gan
2025-01-28 11:55 ` James Clark [this message]
2025-01-29 0:46 ` Jie Gan
2025-01-29 10:35 ` James Clark
2025-01-29 13:02 ` Jie Gan
2025-01-29 14:07 ` James Clark
2025-01-24 7:25 ` [PATCH v9 6/6] arm64: dts: qcom: sa8775p: Add CTCU and ETR nodes Jie Gan
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