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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b65eb036846sm1378295966b.54.2025.10.22.08.13.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Oct 2025 08:13:27 -0700 (PDT) Message-ID: <44ff81bf-8970-475c-a4f5-c03220bc8c3f@oss.qualcomm.com> Date: Wed, 22 Oct 2025 17:13:24 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] drm/msm/a6xx: Add support for Adreno 612 To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang References: <20251017-qcs615-spin-2-v1-0-0baa44f80905@oss.qualcomm.com> <20251017-qcs615-spin-2-v1-1-0baa44f80905@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251017-qcs615-spin-2-v1-1-0baa44f80905@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDIxMDE5MCBTYWx0ZWRfX/rrwaimZkfWr VnYqTAyj0fBjnpb4KikQZigK090Akn2lFzYTRsP28L/gDP5spxrw1Ng0V8ddXm/3GMK1WHwWFrj IOpELE+0tStxfwraBhDHViyZKEZfzhrIArzzUgwxnl1HFcsN0II+8Pm9OphfThiuesTyYFpmzdX 2Ur3SDZqYcX/dqB9BySIzu2j+m1zj8y01E6vWMZGH0KbNehBT+miuuztAqBsga9Ow7441HUvoHR t8LCFew1EjvsxYdTyFeP14qVb2lmntsZSvD6JputzGnVbedjXjIaQaqfue/87mFoQ5/fFpR7s9j yXt5IhCKLJP4VqmyrzdE7wdqvytCkYk9xO8ymgXlIU2H6irOWY2mz5heOLIe/WjPfekXZlwB+8T T53vkvSdhzGbkOouYgonYx5exgZRng== X-Authority-Analysis: v=2.4 cv=FbM6BZ+6 c=1 sm=1 tr=0 ts=68f8f49a cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=NFg73xRieO-LzbxsZPIA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: U1tlOrUwGGC1tItlL6GyYc6Terf1NH34 X-Proofpoint-ORIG-GUID: U1tlOrUwGGC1tItlL6GyYc6Terf1NH34 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_06,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 impostorscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510210190 On 10/17/25 7:08 PM, Akhil P Oommen wrote: > From: Jie Zhang > > Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. > A612 falls under ADRENO_6XX_GEN1 family and is a cut down version > of A615 GPU. > > A612 has a new IP called Reduced Graphics Management Unit or RGMU > which is a small state machine which helps to toggle GX GDSC > (connected to CX rail) to implement IFPC feature. It doesn't support > any other features of a full fledged GMU like clock control, resource > voting to rpmh etc. So we need linux clock driver support like other > gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. > This patch skips RGMU core initialization and act more like a > gmu-wrapper case. > > Co-developed-by: Akhil P Oommen > Signed-off-by: Jie Zhang > Signed-off-by: Akhil P Oommen > --- [...] > @@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { > /* Trigger a OOB (out of band) request to the GMU */ > int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) > { > + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); > + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > int ret; > u32 val; > int request, ack; > > WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); > > + /* Skip OOB calls since RGMU is not enabled */ "RGMU doesn't handle OOB calls" [...] > +int a6xx_rgmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) > +{ > + struct platform_device *pdev = of_find_device_by_node(node); > + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; > + int ret; > + > + if (!pdev) > + return -ENODEV; > + > + gmu->dev = &pdev->dev; > + > + ret = of_dma_configure(gmu->dev, node, true); > + if (ret) > + return ret; > + > + pm_runtime_enable(gmu->dev); > + > + /* Mark legacy for manual SPTPRAC control */ > + gmu->legacy = true; > + > + /* RGMU requires clocks */ > + ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); > + if (ret < 1) > + return ret; Simply add this clock detail to a6xx_gmu_wrapper_init and use _optional [...] > /* Enable fault detection */ > if (adreno_is_a730(adreno_gpu) || > - adreno_is_a740_family(adreno_gpu)) > + adreno_is_a740_family(adreno_gpu) || adreno_is_a612(adreno_gpu)) Sorting this would be neat [...] > +static int a6xx_rgmu_pm_resume(struct msm_gpu *gpu) > +{ > + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); > + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; > + unsigned long freq = gpu->fast_rate; > + struct dev_pm_opp *opp; > + int ret; > + > + gpu->needs_hw_init = true; > + > + trace_msm_gpu_resume(0); > + > + opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); > + if (IS_ERR(opp)) > + return PTR_ERR(opp); > + > + dev_pm_opp_put(opp); > + > + /* Set the core clock and bus bw, having VDD scaling in mind */ > + dev_pm_opp_set_opp(&gpu->pdev->dev, opp); > + > + pm_runtime_resume_and_get(gmu->dev); > + pm_runtime_resume_and_get(gmu->gxpd); > + > + ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); > + if (ret) > + goto err_rpm_put; > + > + ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); > + if (ret) > + goto err_bulk_clk; Add this as-is to a6xx_pm_resume(), nr_clocks==0 is valid, similarly for _suspend Konrad