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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE5MDEzNyBTYWx0ZWRfX/EyEvWmuyfRI EuaCQf/I1Mfm3BloilkW110yrZVARjmzE1qeGvHW/mRzArC6vhvjxDKcNLtFl8jKT1q6Y8Jf9TC 7J8p9t7Ygpcz12ZcQ1fV673kBcJH/OQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE5MDEzNyBTYWx0ZWRfX3aZGeQMUXYJx mbwVMswPPbaBE5pouu1wVTNMvzbMxjnQ7XN5KdTPet8ZN+EHog2SE88QRv+MVai3cVcw57gbo0M HbvnkIR+PSLVC1UaUs15vpaenajXtIPfz1uKJOarmuVQvXPwY05aMBzfUxMR5FJ78nelQuQTgUj FAajAp4lT9vA15Ry0j7SfRk8yQJg1fIfFnDa9yyg+caGhl427m0XBqUSKgnSULIcEw01FuCUwzy 7yw+reHtRAOo37Vi1iL49pClg1hVUV+oMxK/EqKSSRddF/i8hKAzrgw/KMms01pmdDDlPI5xuks 2e1/EaG7wEeerOP85FjWttpRyv+0ctKFvZU+smPwziM2KIcXe1SZQhXs+4J/sz3kwkh86IE9K4x 66qX3ssr29avJD/kwDr3vnBO4TxYbtU6mCxq1TAHIJNo3V+Zz0T5VCyzM43cixkU+aXgpWQGQ9g 3h1EUChZWM1lWSvHQXA== X-Authority-Analysis: v=2.4 cv=H/3rBeYi c=1 sm=1 tr=0 ts=6a3552d3 cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=CBy3kSv35Q_usJoEGC8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 X-Proofpoint-ORIG-GUID: rJ6NqhdESEcVQEA3Uqdq1HoAB3ovMrSJ X-Proofpoint-GUID: rJ6NqhdESEcVQEA3Uqdq1HoAB3ovMrSJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-19_03,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 impostorscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606190137 On 6/18/26 1:37 PM, Marek Szyprowski wrote: > On 16.06.2026 16:31, Marek Szyprowski wrote: >> On 16.06.2026 13:33, Konrad Dybcio wrote: >>> On 3/20/26 12:32 PM, Marek Szyprowski wrote: >>>> On 12.03.2026 12:12, Val Packett wrote: >>>>> Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent >>>>> clocks are enabled during clock operations, preventing potential >>>>> stability issues during display configuration. >>>>> >>>>> Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250") >>>>> Signed-off-by: Val Packett >>>> This patch landed in yesterday's linux-next as commit. In my tests I >>>> found that it triggers the following warning on RB5 board: >>> Hi, I was clearing out my inbox.. Is this still happening on the latest >>> next? >> Yes, still happens here with next-20260615. > > > I've just played a bit with that code and RB5 board and found that this issue > happens, because enabling the DSI PLL clock fails for unknown reason. > > > Here is what happens just before the warnings (I've missed that in the initial > report): > > DSI PLL(0) lock failed, status=0x00000000 > PLL(0) lock failed > > It looks that the generic clock code doesn't take care to properly balance > enable/disable in __clk_set_parent_after() when enabling one of the parent > clock fails in __clk_set_parent_before(). Hm, indeed.. Interestingly the return value of clk_core_prepare_enable() (defined static inside clk.c) is never evaluated, across all of the calls Konrad