Re: [PATCH v3 07/10] phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 9/26/25 1:03 AM, Wesley Cheng wrote:
> 
> 
> On 9/25/2025 3:43 AM, Konrad Dybcio wrote:
>> On 9/25/25 4:28 AM, Wesley Cheng wrote:
>>> For SuperSpeed USB to work properly, there is a set of HW settings that
>>> need to be programmed into the USB blocks within the QMP PHY.  Ensure that
>>> these settings follow the latest settings mentioned in the HW programming
>>> guide.  The QMP USB PHY on Glymur is a USB43 based PHY that will have some
>>> new ways to define certain registers, such as the replacement of TXA/RXA
>>> and TXB/RXB register sets.  This was replaced with the LALB register set.
>>
>> [...]
>>
>>> +    /* override hardware control for reset of qmp phy */
>>> +    if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE])
>>> +        qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1);
>>
>> Clearing this field is going to prevent the PHY from ever going offline
>>
>> The HPG says this should only be necessary for keeping the phy active
>> during MX retention (and the listed usecases are USB4 wakeup clock
>> generation via a respective _USB4 register and/or USB3 autonomous mode
>> operation), both of which are currently unsupported.
>>
>> Are you sure it's necessary / desired?
>>
> 
> Hi Konrad,
> 
> At least on the PHY HSR, its mentioned as required, and if I remember correctly, if this wasn't done, I'd see QMP PHY init timeout.

Hm, the wording in the docs is a little ambiguous to whether
this is really needed, but let's roll with it for now

Konrad