Re: [PATCH v2 3/9] remoteproc: qcom_q6v5_mss: Add MDM9607

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 12/31/25 3:50 PM, barnabas.czeman@mainlining.org wrote:
> On 2025-12-31 13:27, Konrad Dybcio wrote:
>> On 12/31/25 3:29 AM, Barnabás Czémán wrote:
>>> From: Stephan Gerhold <stephan@gerhold.net>
>>>
>>> Add support for MDM9607 MSS it have different ACC settings
>>> and it needs mitigation for inrush current issue.
>>>
>>> Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
>>> [Reword the commit, add has_ext_bhs_reg]
>>> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
>>> ---
>>
>> [...]
>>
>>>              val = readl(qproc->reg_base + mem_pwr_ctl);
>>> -            for (; i >= 0; i--) {
>>> +            for (; i >= reverse; i--) {
>>>                  val |= BIT(i);
>>>                  writel(val, qproc->reg_base + mem_pwr_ctl);
>>>                  /*
>>> @@ -833,6 +847,12 @@ static int q6v5proc_reset(struct q6v5 *qproc)
>>>                  val |= readl(qproc->reg_base + mem_pwr_ctl);
>>>                  udelay(1);
>>>              }
>>> +            for (i = 0; i < reverse; i++) {
>>> +                val |= BIT(i);
>>> +                writel(val, qproc->reg_base + mem_pwr_ctl);
>>> +                val |= readl(qproc->reg_base + mem_pwr_ctl);
>>
>> Downstream doesn't do val |= readl() in the inrush-current-mitigation
>> case
> I have checked you are right, thanks. 1_8 reset sequence have it but 1_8_inrush_current have not.
> As i understanding from downstream it should be handled in both for loop, i could add an if for
> handle this or implement 1_8_inrush_current reset separately. Which one would be the preferred?

Let's do the latter - there's enough nested 'if's in here already

Konrad