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Tue, 14 Oct 2025 03:03:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFaR4sHqbZzJquEl4UlTgUvAbfqjTkOISLr3MINnz0WCArr+8zC5qPyhZB1fBpUV5mZajByaA== X-Received: by 2002:a17:903:910:b0:258:9d26:1860 with SMTP id d9443c01a7336-290273ffeb7mr333722105ad.40.1760436186736; Tue, 14 Oct 2025 03:03:06 -0700 (PDT) Received: from [10.218.33.29] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f87b23sm160005665ad.113.2025.10.14.03.03.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Oct 2025 03:03:06 -0700 (PDT) Message-ID: <486d9339-c7c0-462a-97e2-92a243bbf200@oss.qualcomm.com> Date: Tue, 14 Oct 2025 15:32:42 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] bus: mhi: host: mhi_phc: Add support for PHC over MHI From: Imran Shaik To: Jakub Kicinski , Krishna Chaitanya Chundru Cc: Manivannan Sadhasivam , Richard Cochran , mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, taniya.das@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com References: <20250818-tsc_time_sync-v1-0-2747710693ba@oss.qualcomm.com> <20250818-tsc_time_sync-v1-5-2747710693ba@oss.qualcomm.com> <20250821180247.29d0f4b3@kernel.org> <0b950a45-21e5-4c8d-bc76-1c801b86e2ef@oss.qualcomm.com> Content-Language: en-US In-Reply-To: <0b950a45-21e5-4c8d-bc76-1c801b86e2ef@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDEzMDA4MyBTYWx0ZWRfX5j7IZlXRLdER aX2ie0Qa1WlQybMzZLDkr4Tu7Qxv3uq/jHlJGuRrlg7qFwv7XWD0ClEq4KwlOrp0BmKYiqSdNGN yNPeovBHUuiaNFmv0tQAc+b+YRXJ8+5KjPRA3dlTVNkQkjt1edF6nsKSRRz2luD2FvoovAOdu57 mvkK93gVWKchCercGK/tSThX1fDBB5iX9413yvHRh6YO0Jpl0PRVg7ZIlN98Yd5tIyK/a0KR4yM cKD5elHfimrQwh1TqpJeUwhK/+pfyiCDMalfwIVHdDMbcozNt8DtXY7t3OtdgsRUcfBIw2RaXb5 Wh7hWQiHT+t1BwIzAzuxwmwMZRl2LdGjO3P+nZMuZfimt1MaeNG2ShBKNKqvYqn4lVwZ5X/lrhw wTgfU+h4kfnidDCORxXOqHcpDnMQWg== X-Authority-Analysis: v=2.4 cv=Fr4IPmrq c=1 sm=1 tr=0 ts=68ee1fdc cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=elLdLcMF98_VclgcXSwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: EBiZIKFd7DDE-EFNgJn1GG1Wzqt-4l_f X-Proofpoint-ORIG-GUID: EBiZIKFd7DDE-EFNgJn1GG1Wzqt-4l_f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-14_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510130083 On 9/16/2025 2:47 PM, Imran Shaik wrote: > > > On 8/22/2025 6:32 AM, Jakub Kicinski wrote: >> On Mon, 18 Aug 2025 12:25:50 +0530 Krishna Chaitanya Chundru wrote: >>> This patch introduces the MHI PHC (PTP Hardware Clock) driver, which >>> registers a PTP (Precision Time Protocol) clock and communicates with >>> the MHI core to get the device side timestamps. These timestamps are >>> then exposed to the PTP subsystem, enabling precise time synchronization >>> between the host and the device. >> >>> +static struct ptp_clock_info qcom_ptp_clock_info = { >>> + .owner = THIS_MODULE, >>> + .gettimex64 = qcom_ptp_gettimex64, >>> +}; >> >> Yet another device to device clock sync driver. Please see the >> discussion here: >> https://lore.kernel.org/all/20250815113814.5e135318@kernel.org/ >> I think we have a consensus within the community that we should >> stop cramming random clocks into the PTP subsystem. >> >> Exporting read-only clocks from another processor is not what PTP >> is for. > > Hi Jakub, > > Thank you for the review and for sharing the link to the ongoing discussion. > > I understand the concerns about using the PTP subsystem for read-only clocks. > The idea behind this patch was to use a standard interface for syncing time > between the host and device, and also to make use of existing tools like > phc2sys from userspace. > > I have looked into the on going discussion you pointed, and we’re facing > a similar challenge. Based on internal discussion with the PCIe team, we’ve > confirmed that PCIe PTM isn’t applicable for this hardware use case. > > That said, since it seems the community prefers not to use PTP for such > requirement, could you please suggest any other way to support this time > sync requirement that would be acceptable upstream? > > Appreciate your guidance! > Hi, Could you please share your thoughts on other approaches or directions we could take to support the above requirement in a way that’s acceptable upstream? Thanks, Imran