From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from wolverine01.qualcomm.com ([199.106.114.254]:34375 "EHLO wolverine01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753943Ab0LAQgM (ORCPT ); Wed, 1 Dec 2010 11:36:12 -0500 Message-ID: <4CF6797A.2010807@codeaurora.org> Date: Wed, 01 Dec 2010 11:36:10 -0500 From: Stephen Caudle MIME-Version: 1.0 Subject: Re: [PATCH v2] [ARM] gic: Unmask private interrupts on all cores during IRQ enable References: <1288820762-16077-1-git-send-email-scaudle@codeaurora.org> <20101130180718.GB8521@n2100.arm.linux.org.uk> In-Reply-To: <20101130180718.GB8521@n2100.arm.linux.org.uk> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-arm-msm-owner@vger.kernel.org List-ID: To: Russell King - ARM Linux Cc: dwalker@codeaurora.org, linux-arm-msm@vger.kernel.org, adharmap@codeaurora.org, linux-kernel@vger.kernel.org, miltonm@bga.com, linux-arm-kernel@lists.infradead.org On 11/30/2010 01:07 PM, Russell King - ARM Linux wrote: > Sorry, missed this. > > If it's a private peripheral, it can only be accessed from its associated > CPU. What that means is you don't want to enable the interrupt on other > CPUs as the peripheral may not be present or initialized on that CPU. Understood. But the alternative is to require all code that requests a PPI to have to enable the IRQ on the other cores. This seems unreasonable to me. > So I'm nervous about this change - architecturally it feels like the > wrong thing to do to take the PPI interrupts through the generic IRQ > infrastructure. What do suggest as an alternative to this solution? Creating separate IRQ numbers for each core (per PPI) doesn't seem to scale well as the number of cores increase. ~Stephen -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.