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Tue, 25 Feb 2025 10:08:22 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51PA8L4Y025087 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Feb 2025 10:08:21 GMT Received: from [10.239.29.178] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Feb 2025 02:08:18 -0800 Message-ID: <4a672888-a90e-434c-b494-bb58b91c99a2@quicinc.com> Date: Tue, 25 Feb 2025 18:08:03 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] phy: qcom: qmp-pcie: Add PHY register retention support To: Manivannan Sadhasivam , "Wenbin Yao (Consultant)" CC: Konrad Dybcio , , , , , , , , , , References: <20250220102253.755116-1-quic_wenbyao@quicinc.com> <20250220102253.755116-3-quic_wenbyao@quicinc.com> <20250224073301.aqbw3gxjnupbejfy@thinkpad> <7ffb09cd-9c77-4407-9087-3e789cd8bf44@quicinc.com> <20250224122439.njrcoyrfsisddoer@thinkpad> <20250225081744.3aprpztylrdgs2cl@thinkpad> Content-Language: en-US From: Qiang Yu In-Reply-To: <20250225081744.3aprpztylrdgs2cl@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pZOfpuD-SAPKU2o1hVWkVVh2d7ArKmx9 X-Proofpoint-GUID: pZOfpuD-SAPKU2o1hVWkVVh2d7ArKmx9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_03,2025-02-24_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 malwarescore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502250070 On 2/25/2025 4:17 PM, Manivannan Sadhasivam wrote: > On Tue, Feb 25, 2025 at 04:06:16PM +0800, Wenbin Yao (Consultant) wrote: >> On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: >>> On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: >>>> On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: >>>>> On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: >>>>>> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: >>>>>>> From: Qiang Yu >>>>>>> >>>>>>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>>>>>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>>>>>> but retains register values, which means PHY setting can be skipped during >>>>>>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>>>>>> after that. >>>>>>> >>>>>>> Hence, determine whether the PHY has been enabled in bootloader by >>>>>>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>>>>>> available, skip BCR reset and PHY register setting to establish the PCIe >>>>>>> link with bootloader - programmed PHY settings. >>>>>>> >>>>>>> Signed-off-by: Qiang Yu >>>>>>> Signed-off-by: Wenbin Yao >>>>>> Some nitpicks below. >>>>>> >>>>>>> --- >>>> [...] >>>> >>>>>>> +     * In this way, no matter whether the PHY settings were initially >>>>>>> +     * programmed by bootloader or PHY driver itself, we can reuse them >>>>>> It is really possible to have bootloader not programming the init sequence for >>>>>> no_csr reset platforms? The comment sounds like it is possible. But I heard the >>>>>> opposite. >>>>> PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it >>>>> manually in UEFI shell if we want. >>>> IIUC this will not be a concern going forward, and this is a special case >>>> >>> I'm wondering how many *special* cases we may have to deal with going forward. >>> Anyhow, I would propose to atleast throw an error and fail probe() if: >>> >>> * the platform has no_csr reset AND >>> * bootloader has not initialized the PHY AND >>> * there are no init sequences in the kernel >>> >>> - Mani >> Hmmm, regardless of whether it's a special case, we can't assume that UEFI >> will enable the PHY supporting no_csr reset on all platforms. It's a bit >> risky. If we make such an assumption, we also won't need to check whether >> the PHY is enabled by UEFI during powering on. We just need to check >> whether no_csr reset is available. >> > I am not supportive of this assumption to be clear. While I am OK with relying > on no_csr reset and bootloader programming the PHY, we should also make sure to > catch if the PHY doesn't initialize it. Otherwise, the driver would assume that > the PHY is working, but the users won't see any PCIe devices. > >> But it makes sense to check the exsitence of PHY senquence. How about >> adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't >> initialized in UEFI and there is no cfg->tbls, return error and print some >> error log so that the PCIe controller will fail to probe. >> > Sounds good to me. I'm wondering is it necessary to add this check? In current PHY driver, for PHY that doesn't suppot no_csr reset there is also no such check. If a PHY supports no_csr reset and isn't init in UEFI and there is no cfg->tbls, the worst issue is link training fail and PCIe controller will also fail to probe. Adding sucj check seems not change the result. Thanks, Qiang > > - Mani >