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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fa80cb6sm1076756166b.7.2025.11.17.04.37.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Nov 2025 04:37:48 -0800 (PST) Message-ID: <4b73f64a-1e28-4f25-80d2-3d59575b9da2@oss.qualcomm.com> Date: Mon, 17 Nov 2025 13:37:45 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/3] arm64: dts: qcom: monaco-evk-camera: Add DT overlay To: Nihal Kumar Gupta , Vikram Sharma , bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, hverkuil-cisco@xs4all.nl, cros-qcom-dts-watchers@chromium.org, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, quic_svankada@quicinc.com, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Shankar , Vishal Verma , Vladimir Zapolskiy References: <20251114064541.446276-1-quic_vikramsa@quicinc.com> <20251114064541.446276-4-quic_vikramsa@quicinc.com> <22350774-20da-42ff-a6c2-02fab121f4b5@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <22350774-20da-42ff-a6c2-02fab121f4b5@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=W9U1lBWk c=1 sm=1 tr=0 ts=691b171f cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=7e9gifwXs9hXINWudeUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-GUID: hJLuN3KRmey7iMDJbl6CJ1HydkbrvqLT X-Proofpoint-ORIG-GUID: hJLuN3KRmey7iMDJbl6CJ1HydkbrvqLT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE3MDEwNyBTYWx0ZWRfXw6AwO4xmV8/U SelMcmafltZ9sH788oxQ6n/6uSGDOD6Zb7833MCC9W52wC7HaLGFz8fMSm+p/yXxpwwlhlKLUsQ +4SQuDbbTkiTafXix/97+xQMdIq4MqqggWo8HBx0WJNTwpYwVS4ZCFRC5wRH6BlFcOTQWNpP89W RzO6HDHZxE0jrv1Op43GuCyBNlw7sE8yOMw+P+9XtK1BPq6gT6CldetytVXAU35vwkLQhml+oDX uZ0MQ1GydEyi1L65j8zwMr5ByxZb8w85qxSQlFVWZ33JcGqXF+K4kWnKBaCrdbodBkHnVTh0gOz DkQZeQWAMGGq8CuXGazTR2vRGuyz7zygifzzmoDkwRgoRGb7SLp0kmokSliKidIzbuU4z9Qc5+e v4dbjOwNhb2rRpgB2GaDeytU4dW1QQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-17_03,2025-11-13_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511170107 On 11/15/25 6:53 AM, Nihal Kumar Gupta wrote: > > > On 15-11-2025 03:49, Konrad Dybcio wrote: >>> +&{/} { >>> + vreg_cam1_2p8: vreg-cam1-2p8 { >> Where does this regulator lie physically? Is its presence dependent >> on the connection of the sensor, is it part of the EVK carrier board, >> or perhaps something else? > vreg_cam1_2p8 is a fixed 2.8 V regulator located on the EVK carrier board. > It supplies the camera sensor’s AVDD rail and is enabled via GPIO 74, which is controlled by the TLMM block. Please keep this definition in the EVK board then. It would let one reuse it for another consumer > >> >>> + compatible = "regulator-fixed"; >>> + regulator-name = "vreg_cam1_2p8"; >>> + startup-delay-us = <10000>; >>> + enable-active-high; >>> + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&cam1_avdd_2v8_en_default>; >> property-n >> property-names >> >> please >> > ACK > >> [...] >> >>> +&tlmm { >>> + /* >>> + * gpio67, gpio68, gpio69 provide MCLK0, MCLK1, MCLK2 for >>> + * CAM0, CAM1 and CAM2 respectively via the "cam_mclk" function. >>> + * So, here it's MCLK1 pin for instance. >>> + */ >> I don't really see the value in these comments.. >> >> Vladimir requested you to move the 'description' (meaning the node >> describing the hardware, not a comment explaining the function of the >> DT hunk in natural language) to monaco.dtsi too > I’ve added descriptions to indicate which pins enable which camera MCLK/Regulators. If these aren’t considered useful, I can remove them. Please do > Should I need to add hardware descriptions for all GPIOs (gpio67–69 for MCLK and gpio73–75 for regulator enable), even if they are unused? You're going to need them when you add support for other sensors, so I see no reason why you'd not want to do it right away > I have referenced qcs6490-rb3gen2-vision-mezzanine.dtso for the MCLK pin hardware description (cam1_default). > All TLMM GPIOs mentioned above are muxed pins. As Bryan suggested in v4, these should go into the mezzanine-specific dtso. Do I need to extend this in monaco.dtsi as well? These mux settings apply to any and all users of the mclk function, there is nothing specific to this single mezzanine about it Konrad