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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c739dfbf4fesm11934591a12.0.2026.03.10.03.58.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Mar 2026 03:59:01 -0700 (PDT) Message-ID: <4b92b344-c5ef-4bc1-83dc-5f340c5daa89@oss.qualcomm.com> Date: Tue, 10 Mar 2026 18:58:54 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v14 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices To: Suzuki K Poulose , Jie Gan , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20260309-enable-byte-cntr-for-ctcu-v14-0-c08823e5a8e6@oss.qualcomm.com> <20260309-enable-byte-cntr-for-ctcu-v14-6-c08823e5a8e6@oss.qualcomm.com> <2ac1d8a1-5cda-4e5c-8c6a-ad08d53e3347@arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <2ac1d8a1-5cda-4e5c-8c6a-ad08d53e3347@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=Rcmdyltv c=1 sm=1 tr=0 ts=69aff977 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=Tkd2dFuKn2QnQrKl1zwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDA5NCBTYWx0ZWRfXyNAyRnTfxoTl nYQkaoPk2yej/NAzQcd/DrsVN+hiSq171EgBt1QGSAgAuiJwPLUcPqJdWGWG6oq8zojpEjpjncv Oq6ZI3Uh9fNPK4GBP7GV3PUiL/hy6GtD+qJnzTC7UX1PIxSTM0ZiSqGTwLRbVvpeSTXcyyzeoHx eQZfBRR0z4OuSppx0UbF9wlWNHQqwcLLuDtZ9vPuONfD3JMWFIZ/2M0MLE9rzCxdftz4+DVb29R 6oWyKOOGZHonwAzdina0tuzL6IkHkvQr5j/0H5QcpccsTz/etGFdLo8lGbVMDF3Q4elyh0mTGbl I+/X0FhpKtAQZFuOhHyGprjCU1wX9MsBd+wo5H3H/digJ4YPJc05hC5YK2i+KCqyiUoBbiuY0DE QSPBYV2+J5Nchdn3431s4EH6+INieZXgQGUgcl5n42UG4GtGrKgJ73KCqECDJ4JdKOz2i2GyDRp 7qux7I8YH+MzeSTmDRw== X-Proofpoint-GUID: ZLk8Hx4zKhoBpny49BJ87mEqMnP6fw9w X-Proofpoint-ORIG-GUID: ZLk8Hx4zKhoBpny49BJ87mEqMnP6fw9w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_02,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100094 On 3/10/2026 5:15 PM, Suzuki K Poulose wrote: > On 10/03/2026 03:01, Jie Gan wrote: >> >> >> On 3/9/2026 8:43 PM, Suzuki K Poulose wrote: >>> On 09/03/2026 09:47, Jie Gan wrote: >>>> The byte-cntr function provided by the CTCU device is used to >>>> transfer data >>>> from the ETR buffer to the userspace. An interrupt is triggered if >>>> the data >>>> size exceeds the threshold set in the BYTECNTRVAL register. The >>>> interrupt >>>> handler counts the number of triggered interruptions and the read >>>> function >>>> will read the data from the synced ETR buffer. >>>> >>>> Switching the sysfs_buf when current buffer is full or the timeout is >>>> triggered and resets rrp and rwp registers after switched the buffer. >>>> The synced buffer will become available for reading after the switch. >>>> >>>> Signed-off-by: Jie Gan >>>> --- >>>>   .../ABI/testing/sysfs-bus-coresight-devices-ctcu   |   8 + >>>>   drivers/hwtracing/coresight/Makefile               |   2 +- >>>>   .../hwtracing/coresight/coresight-ctcu-byte-cntr.c | 351 +++++++++ >>>> + + ++++++++++ >>>>   drivers/hwtracing/coresight/coresight-ctcu-core.c  | 103 +++++- >>>>   drivers/hwtracing/coresight/coresight-ctcu.h       |  76 ++++- >>>>   drivers/hwtracing/coresight/coresight-tmc-core.c   |   8 +- >>>>   drivers/hwtracing/coresight/coresight-tmc-etr.c    |  18 ++ >>>>   drivers/hwtracing/coresight/coresight-tmc.h        |   4 + >>>>   8 files changed, 555 insertions(+), 15 deletions(-) >>>> >>>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices- >>>> ctcu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu >>>> new file mode 100644 >>>> index 000000000000..6ff1708fb944 >>>> --- /dev/null >>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu >>>> @@ -0,0 +1,8 @@ >>>> +What:           /sys/bus/coresight/devices// >>>> irq_threshold[0:1] >>>> +Date:           March 2026 >>>> +KernelVersion:  7.1 >>>> +Contact:        Tingwei Zhang ; >>>> Jinlong Mao ; Jie Gan >>>> >>>> +Description: >>>> +        (RW) Configure the byte-cntr IRQ register for the specified >>>> ETR device >>>> +        based on its port number. An interrupt is generated when >>>> the data size >>>> +        exceeds the value set in the IRQ register. >>>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/ >>>> hwtracing/ coresight/Makefile >>>> index ab16d06783a5..821a1b06b20c 100644 >>>> --- a/drivers/hwtracing/coresight/Makefile >>>> +++ b/drivers/hwtracing/coresight/Makefile >>>> @@ -55,5 +55,5 @@ coresight-cti-y := coresight-cti-core.o coresight- >>>> cti-platform.o \ >>>>   obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o >>>>   obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o >>>>   obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o >>>> -coresight-ctcu-y := coresight-ctcu-core.o >>>> +coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o >>>>   obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o >>>> diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c >>>> b/ drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c >>>> new file mode 100644 >>>> index 000000000000..0bf738d6c283 >>>> --- /dev/null >>>> +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c >>>> @@ -0,0 +1,351 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> +/* >>>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include "coresight-ctcu.h" >>>> +#include "coresight-priv.h" >>>> +#include "coresight-tmc.h" >>>> + >>>> +static irqreturn_t byte_cntr_handler(int irq, void *data) >>>> +{ >>>> +    struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr >>>> *)data; >>>> + >>>> +    atomic_inc(&byte_cntr_data->irq_cnt); >>>> +    wake_up(&byte_cntr_data->wq); >>>> + >>>> +    return IRQ_HANDLED; >>>> +} >>>> + >>>> +static void ctcu_reset_sysfs_buf(struct tmc_drvdata *drvdata) >>> >>> minor nit: This has nothing to do with the CTCU. For what it is worth, >>> it must be called, tmc_etr_reset_sysf_buf(). But more on this below, >>> and even do we need it, further below. >>> >>>> +{ >>>> +    u32 sts; >>>> + >>>> +    CS_UNLOCK(drvdata->base); >>>> +    tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr); >>>> +    tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr); >>>> +    sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; >>>> +    writel_relaxed(sts, drvdata->base + TMC_STS); >>>> +    CS_LOCK(drvdata->base); >>> >>> Could we not keep this function in the tmc-etr.c and invoke from here ? >>> >> >> Sure, will move the function tmc-etr.c >> >>>> +} >>>> + >>>> +static void ctcu_cfg_byte_cntr_reg(struct tmc_drvdata *drvdata, u32 >>>> val, u32 offset) >>>> +{ >>>> +    struct ctcu_drvdata *ctcu_drvdata; >>>> +    struct coresight_device *helper; >>>> + >>>> +    helper = tmc_etr_get_ctcu_device(drvdata); >>>> +    if (!helper) >>>> +        return; >>>> + >>>> +    ctcu_drvdata = dev_get_drvdata(helper->dev.parent); >>>> +    /* A one value for IRQCTRL register represents 8 bytes */ >>>> +    ctcu_program_register(ctcu_drvdata, val / 8, offset); >>>> +} >>>> + >>>> +static struct ctcu_byte_cntr *ctcu_get_byte_cntr_data(struct >>>> tmc_drvdata *drvdata) >>>> +{ >>>> +    struct ctcu_byte_cntr *byte_cntr_data; >>>> +    struct ctcu_drvdata *ctcu_drvdata; >>>> +    struct coresight_device *helper; >>>> +    int port; >>>> + >>>> +    helper = tmc_etr_get_ctcu_device(drvdata); >>>> +    if (!helper) >>>> +        return NULL; >>>> + >>> >>> >>> >>>> +    port = coresight_get_in_port(drvdata->csdev, helper); >>>> +    if (port < 0) >>>> +        return NULL; >>>> + >>> >>> Please validate that the port_num you get is valid for the CTCU ? >>> That applies to all uses of this construct. >>> >> >> Will validate it before using. >> >>>> +    ctcu_drvdata = dev_get_drvdata(helper->dev.parent); >>>> +    byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port]; >>>> +    return byte_cntr_data; >>> >>> >>> >>> nit: >>>      return  &ctcu_drvdata->byte_cntr_data[port]; ? >>> >>> Also, why not make this into a helper, as we seem to use this other >>> places too ? >>> >> >> Didnt get the point here. We may run more than one ETR devices >> concurrently. So we should get the proper byte_cntr_data according to >> the port number at runtime. >> > > > static struct ctcu_byte_cntr *ctcu_byte_cntr(struct coresight_device > *cctcu_dev, struct coresight_device *tmc_etr, ) { > >     port = coresight_get_in_port().. >     // Verify the port in this helper and everyone uses this. >     if (//!validate_port//) >         return NULL >     return ... > } Got the point now. I have missed the instance 2/instance 3 you have mentioned in previous message. Thanks, Jie > > > Suzuki > >