* [PATCH v5 1/6] media: qcom: camss: Add support for TFE (Spectra 340)
2025-07-04 8:15 [PATCH v5 0/6] media: qcom: camss: Add qcm2290 support Loic Poulain
@ 2025-07-04 8:15 ` Loic Poulain
2025-07-05 3:24 ` kernel test robot
2025-07-04 8:15 ` [PATCH v5 2/6] media: qcom: camss: Add CSID 340 support Loic Poulain
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Loic Poulain @ 2025-07-04 8:15 UTC (permalink / raw)
To: bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov,
Loic Poulain
Add support for TFE (Thin Front End) found in QCM2290.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
.../media/platform/qcom/camss/camss-vfe-340.c | 319 ++++++++++++++++++
drivers/media/platform/qcom/camss/camss-vfe.h | 1 +
3 files changed, 321 insertions(+)
create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-340.c
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index d26a9c24a430..719898f5d32b 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -17,6 +17,7 @@ qcom-camss-objs += \
camss-vfe-4-7.o \
camss-vfe-4-8.o \
camss-vfe-17x.o \
+ camss-vfe-340.o \
camss-vfe-480.o \
camss-vfe-680.o \
camss-vfe-780.o \
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-340.c b/drivers/media/platform/qcom/camss/camss-vfe-340.c
new file mode 100644
index 000000000000..ab91387b7894
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-vfe-340.c
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module 340 (TFE)
+ *
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#include "camss.h"
+#include "camss-vfe.h"
+
+#define TFE_GLOBAL_RESET_CMD (0x014)
+#define TFE_GLOBAL_RESET_CMD_CORE BIT(0)
+
+#define TFE_REG_UPDATE_CMD (0x02c)
+
+#define TFE_IRQ_CMD (0x030)
+#define TFE_IRQ_CMD_CLEAR BIT(0)
+#define TFE_IRQ_MASK_0 (0x034)
+#define TFE_IRQ_MASK_0_RST_DONE BIT(0)
+#define TFE_IRQ_MASK_0_BUS_WR BIT(1)
+#define TFE_IRQ_MASK_1 (0x038)
+#define TFE_IRQ_MASK_2 (0x03c)
+#define TFE_IRQ_CLEAR_0 (0x040)
+
+#define TFE_IRQ_STATUS_0 (0x04c)
+
+#define BUS_REG(a) (0xa00 + (a))
+
+#define TFE_BUS_IRQ_MASK_0 BUS_REG(0x18)
+#define TFE_BUS_IRQ_MASK_RUP_DONE_MASK GENMASK(3, 0)
+#define TFE_BUS_IRQ_MASK_RUP_DONE(sc) FIELD_PREP(TFE_BUS_IRQ_MASK_RUP_DONE_MASK, BIT(sc))
+#define TFE_BUS_IRQ_MASK_BUF_DONE_MASK GENMASK(15, 8)
+#define TFE_BUS_IRQ_MASK_BUF_DONE(sg) FIELD_PREP(TFE_BUS_IRQ_MASK_BUF_DONE_MASK, BIT(sg))
+#define TFE_BUS_IRQ_MASK_0_CONS_VIOL BIT(28)
+#define TFE_BUS_IRQ_MASK_0_VIOL BIT(30)
+#define TFE_BUS_IRQ_MASK_0_IMG_VIOL BIT(31)
+
+#define TFE_BUS_IRQ_MASK_1 BUS_REG(0x1c)
+#define TFE_BUS_IRQ_CLEAR_0 BUS_REG(0x20)
+#define TFE_BUS_IRQ_STATUS_0 BUS_REG(0x28)
+#define TFE_BUS_IRQ_CMD BUS_REG(0x30)
+#define TFE_BUS_IRQ_CMD_CLEAR BIT(0)
+
+#define TFE_BUS_STATUS_CLEAR BUS_REG(0x60)
+#define TFE_BUS_VIOLATION_STATUS BUS_REG(0x64)
+#define TFE_BUS_OVERFLOW_STATUS BUS_REG(0x68)
+#define TFE_BUS_IMAGE_SZ_VIOLATION_STATUS BUS_REG(0x70)
+
+#define TFE_BUS_CLIENT_CFG(c) BUS_REG(0x200 + (c) * 0x100)
+#define TFE_BUS_CLIENT_CFG_EN BIT(0)
+#define TFE_BUS_CLIENT_CFG_MODE_FRAME BIT(16)
+#define TFE_BUS_IMAGE_ADDR(c) BUS_REG(0x204 + (c) * 0x100)
+#define TFE_BUS_FRAME_INCR(c) BUS_REG(0x208 + (c) * 0x100)
+#define TFE_BUS_IMAGE_CFG_0(c) BUS_REG(0x20c + (c) * 0x100)
+#define TFE_BUS_IMAGE_CFG_0_DEFAULT 0xffff
+#define TFE_BUS_IMAGE_CFG_1(c) BUS_REG(0x210 + (c) * 0x100)
+#define TFE_BUS_IMAGE_CFG_2(c) BUS_REG(0x214 + (c) * 0x100)
+#define TFE_BUS_IMAGE_CFG_2_DEFAULT 0xffff
+#define TFE_BUS_PACKER_CFG(c) BUS_REG(0x218 + (c) * 0x100)
+#define TFE_BUS_PACKER_CFG_FMT_PLAIN64 0xa
+#define TFE_BUS_IRQ_SUBSAMPLE_CFG_0(c) BUS_REG(0x230 + (c) * 0x100)
+#define TFE_BUS_IRQ_SUBSAMPLE_CFG_1(c) BUS_REG(0x234 + (c) * 0x100)
+#define TFE_BUS_FRAMEDROP_CFG_0(c) BUS_REG(0x238 + (c) * 0x100)
+#define TFE_BUS_FRAMEDROP_CFG_1(c) BUS_REG(0x23c + (c) * 0x100)
+
+/*
+ * TODO: differentiate the port id based on requested type of RDI, BHIST etc
+ *
+ * TFE write master IDs (clients)
+ *
+ * BAYER 0
+ * IDEAL_RAW 1
+ * STATS_TINTLESS_BG 2
+ * STATS_BHIST 3
+ * STATS_AWB_BG 4
+ * STATS_AEC_BG 5
+ * STATS_BAF 6
+ * RDI0 7
+ * RDI1 8
+ * RDI2 9
+ */
+#define RDI_WM(n) (7 + (n))
+#define TFE_WM_NUM 10
+
+enum tfe_iface {
+ TFE_IFACE_PIX,
+ TFE_IFACE_RDI0,
+ TFE_IFACE_RDI1,
+ TFE_IFACE_RDI2,
+ TFE_IFACE_NUM
+};
+
+enum tfe_subgroups {
+ TFE_SUBGROUP_BAYER,
+ TFE_SUBGROUP_IDEAL_RAW,
+ TFE_SUBGROUP_HDR,
+ TFE_SUBGROUP_BG,
+ TFE_SUBGROUP_BAF,
+ TFE_SUBGROUP_RDI0,
+ TFE_SUBGROUP_RDI1,
+ TFE_SUBGROUP_RDI2,
+ TFE_SUBGROUP_NUM
+};
+
+enum tfe_iface tfe_line_iface_map[VFE_LINE_NUM_MAX] = {
+ [VFE_LINE_RDI0] = TFE_IFACE_RDI0,
+ [VFE_LINE_RDI1] = TFE_IFACE_RDI1,
+ [VFE_LINE_RDI2] = TFE_IFACE_RDI2,
+ [VFE_LINE_PIX] = TFE_IFACE_PIX,
+};
+
+enum vfe_line_id tfe_subgroup_line_map[TFE_SUBGROUP_NUM] = {
+ [TFE_SUBGROUP_BAYER] = VFE_LINE_PIX,
+ [TFE_SUBGROUP_IDEAL_RAW] = VFE_LINE_PIX,
+ [TFE_SUBGROUP_HDR] = VFE_LINE_PIX,
+ [TFE_SUBGROUP_BG] = VFE_LINE_PIX,
+ [TFE_SUBGROUP_BAF] = VFE_LINE_PIX,
+ [TFE_SUBGROUP_RDI0] = VFE_LINE_RDI0,
+ [TFE_SUBGROUP_RDI1] = VFE_LINE_RDI1,
+ [TFE_SUBGROUP_RDI2] = VFE_LINE_RDI2,
+};
+
+static inline enum tfe_iface __line_to_iface(enum vfe_line_id line_id)
+{
+ if (line_id <= VFE_LINE_NONE || line_id >= VFE_LINE_NUM_MAX) {
+ pr_warn("VFE: Invalid line %d\n", line_id);
+ return TFE_IFACE_RDI0;
+ }
+
+ return tfe_line_iface_map[line_id];
+}
+
+static inline enum vfe_line_id __iface_to_line(unsigned int iface)
+{
+ int i;
+
+ for (i = 0; i < VFE_LINE_NUM_MAX; i++) {
+ if (tfe_line_iface_map[i] == iface)
+ return i;
+ }
+
+ return VFE_LINE_NONE;
+}
+
+static inline enum vfe_line_id __subgroup_to_line(enum tfe_subgroups sg)
+{
+ if (sg >= TFE_SUBGROUP_NUM)
+ return VFE_LINE_NONE;
+
+ return tfe_subgroup_line_map[sg];
+}
+
+static void vfe_global_reset(struct vfe_device *vfe)
+{
+ writel(TFE_IRQ_MASK_0_RST_DONE, vfe->base + TFE_IRQ_MASK_0);
+ writel(TFE_GLOBAL_RESET_CMD_CORE, vfe->base + TFE_GLOBAL_RESET_CMD);
+}
+
+static irqreturn_t vfe_isr(int irq, void *dev)
+{
+ struct vfe_device *vfe = dev;
+ u32 status;
+ int i;
+
+ status = readl_relaxed(vfe->base + TFE_IRQ_STATUS_0);
+ writel_relaxed(status, vfe->base + TFE_IRQ_CLEAR_0);
+ writel_relaxed(TFE_IRQ_CMD_CLEAR, vfe->base + TFE_IRQ_CMD);
+
+ if (status & TFE_IRQ_MASK_0_RST_DONE) {
+ dev_dbg(vfe->camss->dev, "VFE%u: Reset done!", vfe->id);
+ vfe_isr_reset_ack(vfe);
+ }
+
+ if (status & TFE_IRQ_MASK_0_BUS_WR) {
+ u32 bus_status = readl_relaxed(vfe->base + TFE_BUS_IRQ_STATUS_0);
+
+ writel_relaxed(bus_status, vfe->base + TFE_BUS_IRQ_CLEAR_0);
+ writel_relaxed(TFE_BUS_IRQ_CMD_CLEAR, vfe->base + TFE_BUS_IRQ_CMD);
+
+ for (i = 0; i < TFE_IFACE_NUM; i++) {
+ if (bus_status & TFE_BUS_IRQ_MASK_RUP_DONE(i))
+ vfe->res->hw_ops->reg_update_clear(vfe, __iface_to_line(i));
+ }
+
+ for (i = 0; i < TFE_SUBGROUP_NUM; i++) {
+ if (bus_status & TFE_BUS_IRQ_MASK_BUF_DONE(i))
+ vfe_buf_done(vfe, __subgroup_to_line(i));
+ }
+
+ if (bus_status & TFE_BUS_IRQ_MASK_0_CONS_VIOL)
+ dev_err_ratelimited(vfe->camss->dev, "VFE%u: Bad config violation",
+ vfe->id);
+
+ if (bus_status & TFE_BUS_IRQ_MASK_0_VIOL)
+ dev_err_ratelimited(vfe->camss->dev, "VFE%u: Input data violation",
+ vfe->id);
+
+ if (bus_status & TFE_BUS_IRQ_MASK_0_IMG_VIOL)
+ dev_err_ratelimited(vfe->camss->dev, "VFE%u: Image size violation",
+ vfe->id);
+ }
+
+ status = readl_relaxed(vfe->base + TFE_BUS_OVERFLOW_STATUS);
+ if (status) {
+ writel_relaxed(status, vfe->base + TFE_BUS_STATUS_CLEAR);
+ for (i = 0; i < TFE_WM_NUM; i++) {
+ if (status & BIT(i))
+ dev_err_ratelimited(vfe->camss->dev,
+ "VFE%u: bus overflow for wm %u\n",
+ vfe->id, i);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int vfe_halt(struct vfe_device *vfe)
+{
+ /* rely on vfe_disable_output() to stop the VFE */
+ return 0;
+}
+
+static void vfe_enable_irq(struct vfe_device *vfe)
+{
+ writel(TFE_IRQ_MASK_0_RST_DONE | TFE_IRQ_MASK_0_BUS_WR,
+ vfe->base + TFE_IRQ_MASK_0);
+ writel(TFE_BUS_IRQ_MASK_RUP_DONE_MASK | TFE_BUS_IRQ_MASK_BUF_DONE_MASK |
+ TFE_BUS_IRQ_MASK_0_CONS_VIOL | TFE_BUS_IRQ_MASK_0_VIOL |
+ TFE_BUS_IRQ_MASK_0_IMG_VIOL, vfe->base + TFE_BUS_IRQ_MASK_0);
+}
+
+static void vfe_wm_update(struct vfe_device *vfe, u8 rdi, u32 addr,
+ struct vfe_line *line)
+{
+ u8 wm = RDI_WM(rdi);
+
+ writel_relaxed(addr, vfe->base + TFE_BUS_IMAGE_ADDR(wm));
+}
+
+static void vfe_wm_start(struct vfe_device *vfe, u8 rdi, struct vfe_line *line)
+{
+ struct v4l2_pix_format_mplane *pix = &line->video_out.active_fmt.fmt.pix_mp;
+ u32 stride = pix->plane_fmt[0].bytesperline;
+ u8 wm = RDI_WM(rdi);
+
+ /* Configuration for plain RDI frames */
+ writel_relaxed(TFE_BUS_IMAGE_CFG_0_DEFAULT, vfe->base + TFE_BUS_IMAGE_CFG_0(wm));
+ writel_relaxed(0u, vfe->base + TFE_BUS_IMAGE_CFG_1(wm));
+ writel_relaxed(TFE_BUS_IMAGE_CFG_2_DEFAULT, vfe->base + TFE_BUS_IMAGE_CFG_2(wm));
+ writel_relaxed(stride * pix->height, vfe->base + TFE_BUS_FRAME_INCR(wm));
+ writel_relaxed(TFE_BUS_PACKER_CFG_FMT_PLAIN64, vfe->base + TFE_BUS_PACKER_CFG(wm));
+
+ /* No dropped frames, one irq per frame */
+ writel_relaxed(0, vfe->base + TFE_BUS_FRAMEDROP_CFG_0(wm));
+ writel_relaxed(1, vfe->base + TFE_BUS_FRAMEDROP_CFG_1(wm));
+ writel_relaxed(0, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_0(wm));
+ writel_relaxed(1, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_1(wm));
+
+ vfe_enable_irq(vfe);
+
+ writel(TFE_BUS_CLIENT_CFG_EN | TFE_BUS_CLIENT_CFG_MODE_FRAME,
+ vfe->base + TFE_BUS_CLIENT_CFG(wm));
+
+ dev_dbg(vfe->camss->dev, "VFE%u: Started RDI%u width %u height %u stride %u\n",
+ vfe->id, rdi, pix->width, pix->height, stride);
+}
+
+static void vfe_wm_stop(struct vfe_device *vfe, u8 rdi)
+{
+ u8 wm = RDI_WM(rdi);
+
+ writel(0, vfe->base + TFE_BUS_CLIENT_CFG(wm));
+
+ dev_dbg(vfe->camss->dev, "VFE%u: Stopped RDI%u\n", vfe->id, rdi);
+}
+
+static const struct camss_video_ops vfe_video_ops_520 = {
+ .queue_buffer = vfe_queue_buffer_v2,
+ .flush_buffers = vfe_flush_buffers,
+};
+
+static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
+{
+ vfe->video_ops = vfe_video_ops_520;
+}
+
+static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ vfe->reg_update |= BIT(__line_to_iface(line_id));
+ writel_relaxed(vfe->reg_update, vfe->base + TFE_REG_UPDATE_CMD);
+}
+
+static void vfe_reg_update_clear(struct vfe_device *vfe, enum vfe_line_id line_id)
+{
+ vfe->reg_update &= ~BIT(__line_to_iface(line_id));
+}
+
+const struct vfe_hw_ops vfe_ops_340 = {
+ .global_reset = vfe_global_reset,
+ .hw_version = vfe_hw_version,
+ .isr = vfe_isr,
+ .pm_domain_off = vfe_pm_domain_off,
+ .pm_domain_on = vfe_pm_domain_on,
+ .subdev_init = vfe_subdev_init,
+ .vfe_disable = vfe_disable,
+ .vfe_enable = vfe_enable_v2,
+ .vfe_halt = vfe_halt,
+ .vfe_wm_start = vfe_wm_start,
+ .vfe_wm_stop = vfe_wm_stop,
+ .vfe_buf_done = vfe_buf_done,
+ .vfe_wm_update = vfe_wm_update,
+ .reg_update = vfe_reg_update,
+ .reg_update_clear = vfe_reg_update_clear,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index a23f666be753..9b138849caca 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -242,6 +242,7 @@ extern const struct vfe_hw_ops vfe_ops_4_1;
extern const struct vfe_hw_ops vfe_ops_4_7;
extern const struct vfe_hw_ops vfe_ops_4_8;
extern const struct vfe_hw_ops vfe_ops_170;
+extern const struct vfe_hw_ops vfe_ops_340;
extern const struct vfe_hw_ops vfe_ops_480;
extern const struct vfe_hw_ops vfe_ops_680;
extern const struct vfe_hw_ops vfe_ops_780;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v5 1/6] media: qcom: camss: Add support for TFE (Spectra 340)
2025-07-04 8:15 ` [PATCH v5 1/6] media: qcom: camss: Add support for TFE (Spectra 340) Loic Poulain
@ 2025-07-05 3:24 ` kernel test robot
0 siblings, 0 replies; 10+ messages in thread
From: kernel test robot @ 2025-07-05 3:24 UTC (permalink / raw)
To: Loic Poulain, bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: llvm, oe-kbuild-all, linux-arm-msm, linux-media, devicetree,
dmitry.baryshkov, Loic Poulain
Hi Loic,
kernel test robot noticed the following build errors:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.16-rc4 next-20250704]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Loic-Poulain/media-qcom-camss-Add-support-for-TFE-Spectra-340/20250704-163126
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20250704081537.1716613-2-loic.poulain%40oss.qualcomm.com
patch subject: [PATCH v5 1/6] media: qcom: camss: Add support for TFE (Spectra 340)
config: hexagon-allmodconfig (https://download.01.org/0day-ci/archive/20250705/202507051109.lDPTfVhw-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250705/202507051109.lDPTfVhw-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202507051109.lDPTfVhw-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/media/platform/qcom/camss/camss-vfe-340.c:186:21: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
186 | if (bus_status & TFE_BUS_IRQ_MASK_RUP_DONE(i))
| ^
drivers/media/platform/qcom/camss/camss-vfe-340.c:36:40: note: expanded from macro 'TFE_BUS_IRQ_MASK_RUP_DONE'
36 | #define TFE_BUS_IRQ_MASK_RUP_DONE(sc) FIELD_PREP(TFE_BUS_IRQ_MASK_RUP_DONE_MASK, BIT(sc))
| ^
drivers/media/platform/qcom/camss/camss-vfe-340.c:191:21: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
191 | if (bus_status & TFE_BUS_IRQ_MASK_BUF_DONE(i))
| ^
drivers/media/platform/qcom/camss/camss-vfe-340.c:38:40: note: expanded from macro 'TFE_BUS_IRQ_MASK_BUF_DONE'
38 | #define TFE_BUS_IRQ_MASK_BUF_DONE(sg) FIELD_PREP(TFE_BUS_IRQ_MASK_BUF_DONE_MASK, BIT(sg))
| ^
2 errors generated.
vim +/FIELD_PREP +186 drivers/media/platform/qcom/camss/camss-vfe-340.c
163
164 static irqreturn_t vfe_isr(int irq, void *dev)
165 {
166 struct vfe_device *vfe = dev;
167 u32 status;
168 int i;
169
170 status = readl_relaxed(vfe->base + TFE_IRQ_STATUS_0);
171 writel_relaxed(status, vfe->base + TFE_IRQ_CLEAR_0);
172 writel_relaxed(TFE_IRQ_CMD_CLEAR, vfe->base + TFE_IRQ_CMD);
173
174 if (status & TFE_IRQ_MASK_0_RST_DONE) {
175 dev_dbg(vfe->camss->dev, "VFE%u: Reset done!", vfe->id);
176 vfe_isr_reset_ack(vfe);
177 }
178
179 if (status & TFE_IRQ_MASK_0_BUS_WR) {
180 u32 bus_status = readl_relaxed(vfe->base + TFE_BUS_IRQ_STATUS_0);
181
182 writel_relaxed(bus_status, vfe->base + TFE_BUS_IRQ_CLEAR_0);
183 writel_relaxed(TFE_BUS_IRQ_CMD_CLEAR, vfe->base + TFE_BUS_IRQ_CMD);
184
185 for (i = 0; i < TFE_IFACE_NUM; i++) {
> 186 if (bus_status & TFE_BUS_IRQ_MASK_RUP_DONE(i))
187 vfe->res->hw_ops->reg_update_clear(vfe, __iface_to_line(i));
188 }
189
190 for (i = 0; i < TFE_SUBGROUP_NUM; i++) {
191 if (bus_status & TFE_BUS_IRQ_MASK_BUF_DONE(i))
192 vfe_buf_done(vfe, __subgroup_to_line(i));
193 }
194
195 if (bus_status & TFE_BUS_IRQ_MASK_0_CONS_VIOL)
196 dev_err_ratelimited(vfe->camss->dev, "VFE%u: Bad config violation",
197 vfe->id);
198
199 if (bus_status & TFE_BUS_IRQ_MASK_0_VIOL)
200 dev_err_ratelimited(vfe->camss->dev, "VFE%u: Input data violation",
201 vfe->id);
202
203 if (bus_status & TFE_BUS_IRQ_MASK_0_IMG_VIOL)
204 dev_err_ratelimited(vfe->camss->dev, "VFE%u: Image size violation",
205 vfe->id);
206 }
207
208 status = readl_relaxed(vfe->base + TFE_BUS_OVERFLOW_STATUS);
209 if (status) {
210 writel_relaxed(status, vfe->base + TFE_BUS_STATUS_CLEAR);
211 for (i = 0; i < TFE_WM_NUM; i++) {
212 if (status & BIT(i))
213 dev_err_ratelimited(vfe->camss->dev,
214 "VFE%u: bus overflow for wm %u\n",
215 vfe->id, i);
216 }
217 }
218
219 return IRQ_HANDLED;
220 }
221
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v5 2/6] media: qcom: camss: Add CSID 340 support
2025-07-04 8:15 [PATCH v5 0/6] media: qcom: camss: Add qcm2290 support Loic Poulain
2025-07-04 8:15 ` [PATCH v5 1/6] media: qcom: camss: Add support for TFE (Spectra 340) Loic Poulain
@ 2025-07-04 8:15 ` Loic Poulain
2025-07-04 8:15 ` [PATCH v5 3/6] media: qcom: camss: csiphy-3ph: Add CSIPHY 2ph DPHY v2.0.1 init sequence Loic Poulain
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Loic Poulain @ 2025-07-04 8:15 UTC (permalink / raw)
To: bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov,
Loic Poulain
Add support for CSID found in QCM2290, it's a simplified gen-2 version.
- There is no Test Pattern Generator (moved outside CSID)
- There is no subsampling (moved to CAMIF module)
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
.../platform/qcom/camss/camss-csid-340.c | 189 ++++++++++++++++++
.../media/platform/qcom/camss/camss-csid.h | 1 +
3 files changed, 191 insertions(+)
create mode 100644 drivers/media/platform/qcom/camss/camss-csid-340.c
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 719898f5d32b..3217bf40976d 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -6,6 +6,7 @@ qcom-camss-objs += \
camss-csid.o \
camss-csid-4-1.o \
camss-csid-4-7.o \
+ camss-csid-340.o \
camss-csid-680.o \
camss-csid-gen2.o \
camss-csid-780.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-340.c b/drivers/media/platform/qcom/camss/camss-csid-340.c
new file mode 100644
index 000000000000..7a8fbae3009b
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-340.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module 340
+ *
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include "camss.h"
+#include "camss-csid.h"
+#include "camss-csid-gen2.h"
+
+#define CSID_RST_STROBES (0x010)
+#define CSID_RST_SW_REGS BIT(0)
+#define CSID_RST_IRQ BIT(1)
+#define CSID_RST_IFE_CLK BIT(2)
+#define CSID_RST_PHY_CLK BIT(3)
+#define CSID_RST_CSID_CLK BIT(4)
+
+#define CSID_IRQ_STATUS (0x070)
+#define CSID_IRQ_MASK (0x074)
+#define CSID_IRQ_MASK_RST_DONE BIT(0)
+#define CSID_IRQ_CLEAR (0x078)
+#define CSID_IRQ_CMD (0x080)
+#define CSID_IRQ_CMD_CLEAR BIT(0)
+
+#define CSID_CSI2_RX_CFG0 (0x100)
+#define CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK GENMASK(1, 0)
+#define CSI2_RX_CFG0_DLX_INPUT_SEL_MASK GENMASK(17, 4)
+#define CSI2_RX_CFG0_PHY_NUM_SEL_MASK GENMASK(21, 20)
+#define CSI2_RX_CFG0_PHY_NUM_SEL_BASE_IDX 1
+#define CSI2_RX_CFG0_PHY_TYPE_SEL BIT(24)
+
+#define CSID_CSI2_RX_CFG1 (0x104)
+#define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN BIT(0)
+#define CSI2_RX_CFG1_MISR_EN BIT(6)
+#define CSI2_RX_CFG1_CGC_MODE BIT(7)
+
+#define CSID_RDI_CFG0(rdi) (0x300 + 0x100 * (rdi))
+#define CSID_RDI_CFG0_BYTE_CNTR_EN BIT(0)
+#define CSID_RDI_CFG0_TIMESTAMP_EN BIT(1)
+#define CSID_RDI_CFG0_DECODE_FORMAT_MASK GENMASK(15, 12)
+#define CSID_RDI_CFG0_DECODE_FORMAT_NOP CSID_RDI_CFG0_DECODE_FORMAT_MASK
+#define CSID_RDI_CFG0_DT_MASK GENMASK(21, 16)
+#define CSID_RDI_CFG0_VC_MASK GENMASK(23, 22)
+#define CSID_RDI_CFG0_DTID_MASK GENMASK(28, 27)
+#define CSID_RDI_CFG0_ENABLE BIT(31)
+
+#define CSID_RDI_CTRL(rdi) (0x308 + 0x100 * (rdi))
+#define CSID_RDI_CTRL_HALT_AT_FRAME_BOUNDARY 0
+#define CSID_RDI_CTRL_RESUME_AT_FRAME_BOUNDARY 1
+
+static void __csid_configure_rx(struct csid_device *csid,
+ struct csid_phy_config *phy, int vc)
+{
+ u32 val;
+
+ val = FIELD_PREP(CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK, phy->lane_cnt - 1);
+ val |= FIELD_PREP(CSI2_RX_CFG0_DLX_INPUT_SEL_MASK, phy->lane_assign);
+ val |= FIELD_PREP(CSI2_RX_CFG0_PHY_NUM_SEL_MASK,
+ phy->csiphy_id + CSI2_RX_CFG0_PHY_NUM_SEL_BASE_IDX);
+ writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
+
+ val = CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
+ writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
+}
+
+static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
+{
+ writel_relaxed(!!enable, csid->base + CSID_RDI_CTRL(rdi));
+}
+
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
+{
+ struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
+ const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
+ csid->res->formats->nformats,
+ input_format->code);
+ u8 lane_cnt = csid->phy.lane_cnt;
+ u8 dt_id;
+ u32 val;
+
+ if (!lane_cnt)
+ lane_cnt = 4;
+
+ /*
+ * DT_ID is a two bit bitfield that is concatenated with
+ * the four least significant bits of the five bit VC
+ * bitfield to generate an internal CID value.
+ *
+ * CSID_RDI_CFG0(vc)
+ * DT_ID : 28:27
+ * VC : 26:22
+ * DT : 21:16
+ *
+ * CID : VC 3:0 << 2 | DT_ID 1:0
+ */
+ dt_id = vc & 0x03;
+
+ val = CSID_RDI_CFG0_DECODE_FORMAT_NOP; /* only for RDI path */
+ val |= FIELD_PREP(CSID_RDI_CFG0_DT_MASK, format->data_type);
+ val |= FIELD_PREP(CSID_RDI_CFG0_VC_MASK, vc);
+ val |= FIELD_PREP(CSID_RDI_CFG0_DTID_MASK, dt_id);
+
+ if (enable)
+ val |= CSID_RDI_CFG0_ENABLE;
+
+ dev_dbg(csid->camss->dev, "CSID%u: Stream %s (dt:0x%x vc=%u)\n",
+ csid->id, enable ? "enable" : "disable", format->data_type, vc);
+
+ writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
+}
+
+static void csid_configure_stream(struct csid_device *csid, u8 enable)
+{
+ int i;
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ __csid_configure_rdi_stream(csid, enable, i);
+ __csid_configure_rx(csid, &csid->phy, i);
+ __csid_ctrl_rdi(csid, enable, i);
+ }
+ }
+}
+
+static int csid_reset(struct csid_device *csid)
+{
+ unsigned long time;
+
+ writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_MASK);
+ writel_relaxed(CSID_IRQ_MASK_RST_DONE, csid->base + CSID_IRQ_CLEAR);
+ writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
+
+ reinit_completion(&csid->reset_complete);
+
+ /* Reset with registers preserved */
+ writel(CSID_RST_IRQ | CSID_RST_IFE_CLK | CSID_RST_PHY_CLK | CSID_RST_CSID_CLK,
+ csid->base + CSID_RST_STROBES);
+
+ time = wait_for_completion_timeout(&csid->reset_complete,
+ msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
+ if (!time) {
+ dev_err(csid->camss->dev, "CSID%u: reset timeout\n", csid->id);
+ return -EIO;
+ }
+
+ dev_dbg(csid->camss->dev, "CSID%u: reset done\n", csid->id);
+
+ return 0;
+}
+
+static irqreturn_t csid_isr(int irq, void *dev)
+{
+ struct csid_device *csid = dev;
+ u32 val;
+
+ val = readl_relaxed(csid->base + CSID_IRQ_STATUS);
+ writel_relaxed(val, csid->base + CSID_IRQ_CLEAR);
+ writel_relaxed(CSID_IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD);
+
+ if (val & CSID_IRQ_MASK_RST_DONE)
+ complete(&csid->reset_complete);
+ else
+ dev_warn_ratelimited(csid->camss->dev, "Spurious CSID interrupt\n");
+
+ return IRQ_HANDLED;
+}
+
+static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
+{
+ return -EOPNOTSUPP; /* Not part of CSID */
+}
+
+static void csid_subdev_init(struct csid_device *csid) {}
+
+const struct csid_hw_ops csid_ops_340 = {
+ .configure_testgen_pattern = csid_configure_testgen_pattern,
+ .configure_stream = csid_configure_stream,
+ .hw_version = csid_hw_version,
+ .isr = csid_isr,
+ .reset = csid_reset,
+ .src_pad_code = csid_src_pad_code,
+ .subdev_init = csid_subdev_init,
+};
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index 9dc826d8c8f6..3399e92658d8 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -213,6 +213,7 @@ extern const struct csid_formats csid_formats_gen2;
extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
+extern const struct csid_hw_ops csid_ops_340;
extern const struct csid_hw_ops csid_ops_680;
extern const struct csid_hw_ops csid_ops_gen2;
extern const struct csid_hw_ops csid_ops_780;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v5 3/6] media: qcom: camss: csiphy-3ph: Add CSIPHY 2ph DPHY v2.0.1 init sequence
2025-07-04 8:15 [PATCH v5 0/6] media: qcom: camss: Add qcm2290 support Loic Poulain
2025-07-04 8:15 ` [PATCH v5 1/6] media: qcom: camss: Add support for TFE (Spectra 340) Loic Poulain
2025-07-04 8:15 ` [PATCH v5 2/6] media: qcom: camss: Add CSID 340 support Loic Poulain
@ 2025-07-04 8:15 ` Loic Poulain
2025-07-04 8:15 ` [PATCH v5 4/6] media: qcom: camss: add support for QCM2290 camss Loic Poulain
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Loic Poulain @ 2025-07-04 8:15 UTC (permalink / raw)
To: bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov,
Loic Poulain
This is the CSI PHY version found in QCS2290/QCM2290 SoCs.
The table is extracted from downstream camera driver.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../qcom/camss/camss-csiphy-3ph-1-0.c | 89 +++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 90 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index f732a76de93e..91cd697083ff 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -319,6 +319,90 @@ csiphy_lane_regs lane_regs_sm8250[] = {
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
};
+/* 14nm 2PH v 2.0.1 2p5Gbps 4 lane DPHY mode */
+static const struct
+csiphy_lane_regs lane_regs_qcm2290[] = {
+ {0x0030, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x002c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0034, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0028, 0x04, 0x00, CSIPHY_DNP_PARAMS},
+ {0x003c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x001c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0xd7, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0004, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x000c, 0xff, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0038, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0064, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0730, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x072c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0734, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x073c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x071c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0700, 0xc0, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0704, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x070c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0738, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0764, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0230, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x022c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0234, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0228, 0x04, 0x00, CSIPHY_DNP_PARAMS},
+ {0x023c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x021c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0200, 0xd7, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0204, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x020c, 0xff, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0238, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0264, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0430, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x042c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0434, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0428, 0x04, 0x00, CSIPHY_DNP_PARAMS},
+ {0x043c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x041c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0400, 0xd7, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0404, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x040C, 0xff, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0438, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0464, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0630, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x062c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0634, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0628, 0x04, 0x00, CSIPHY_DNP_PARAMS},
+ {0x063c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x061c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0600, 0xd7, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0604, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x060C, 0xff, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0638, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0664, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
/* GEN2 2.1.2 2PH DPHY mode */
static const struct
csiphy_lane_regs lane_regs_sm8550[] = {
@@ -744,6 +828,7 @@ static bool csiphy_is_gen2(u32 version)
bool ret = false;
switch (version) {
+ case CAMSS_2290:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
@@ -829,6 +914,10 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_regs = &lane_regs_sdm845[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
break;
+ case CAMSS_2290:
+ regs->lane_regs = &lane_regs_qcm2290[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
+ break;
case CAMSS_7280:
case CAMSS_8250:
regs->lane_regs = &lane_regs_sm8250[0];
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 63c0afee154a..377707d91ff2 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -78,6 +78,7 @@ enum pm_domain {
enum camss_version {
CAMSS_660,
+ CAMSS_2290,
CAMSS_7280,
CAMSS_8x16,
CAMSS_8x53,
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v5 4/6] media: qcom: camss: add support for QCM2290 camss
2025-07-04 8:15 [PATCH v5 0/6] media: qcom: camss: Add qcm2290 support Loic Poulain
` (2 preceding siblings ...)
2025-07-04 8:15 ` [PATCH v5 3/6] media: qcom: camss: csiphy-3ph: Add CSIPHY 2ph DPHY v2.0.1 init sequence Loic Poulain
@ 2025-07-04 8:15 ` Loic Poulain
2025-07-04 8:15 ` [PATCH v5 5/6] media: dt-bindings: Add qcom,qcm2290-camss Loic Poulain
2025-07-04 8:15 ` [PATCH v5 6/6] arm64: dts: qcom: qcm2290: Add CAMSS node Loic Poulain
5 siblings, 0 replies; 10+ messages in thread
From: Loic Poulain @ 2025-07-04 8:15 UTC (permalink / raw)
To: bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov,
Loic Poulain
The camera subsystem for QCM2290 which is based on Spectra 340.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 148 ++++++++++++++++++
2 files changed, 150 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 4bca6c3abaff..c575c9767492 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -340,6 +340,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
}
break;
case CAMSS_660:
+ case CAMSS_2290:
case CAMSS_7280:
case CAMSS_8x96:
case CAMSS_8250:
@@ -1969,6 +1970,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
+ case CAMSS_2290:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 06f42875702f..6d5b954b08c7 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -515,6 +515,140 @@ static const struct camss_subdev_resources vfe_res_8x96[] = {
}
};
+static const struct camss_subdev_resources csiphy_res_2290[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdd-csiphy-1p2", "vdd-csiphy-1p8" },
+ .clock = { "top_ahb", "ahb", "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 240000000, 341330000, 384000000 },
+ { 100000000, 200000000, 268800000 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdd-csiphy-1p2", "vdd-csiphy-1p8" },
+ .clock = { "top_ahb", "ahb", "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 240000000, 341330000, 384000000 },
+ { 100000000, 200000000, 268800000 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ }
+};
+
+static const struct camss_subdev_resources csid_res_2290[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ahb", "csi0", "vfe0_cphy_rx", "vfe0" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 192000000, 240000000, 384000000, 426400000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .hw_ops = &csid_ops_340,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ahb", "csi1", "vfe1_cphy_rx", "vfe1" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 192000000, 240000000, 384000000, 426400000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .hw_ops = &csid_ops_340,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
+static const struct camss_subdev_resources vfe_res_2290[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ahb", "axi", "vfe0", "camnoc_rt_axi", "camnoc_nrt_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 153600000, 192000000, 256000000, 384000000, 460800000 },
+ { 0 },
+ { 0 }, },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 4,
+ .hw_ops = &vfe_ops_340,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "top_ahb", "ahb", "axi", "vfe1", "camnoc_rt_axi", "camnoc_nrt_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 0 },
+ { 19200000, 153600000, 192000000, 256000000, 384000000, 460800000 },
+ { 0 },
+ { 0 }, },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 4,
+ .hw_ops = &vfe_ops_340,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct resources_icc icc_res_2290[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 3000000,
+ },
+ {
+ .name = "sf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 3000000,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_660[] = {
/* CSIPHY0 */
{
@@ -3753,6 +3887,19 @@ static const struct camss_resources msm8996_resources = {
.link_entities = camss_link_entities
};
+static const struct camss_resources qcm2290_resources = {
+ .version = CAMSS_2290,
+ .csiphy_res = csiphy_res_2290,
+ .csid_res = csid_res_2290,
+ .vfe_res = vfe_res_2290,
+ .icc_res = icc_res_2290,
+ .icc_path_num = ARRAY_SIZE(icc_res_2290),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_2290),
+ .csid_num = ARRAY_SIZE(csid_res_2290),
+ .vfe_num = ARRAY_SIZE(vfe_res_2290),
+ .link_entities = camss_link_entities
+};
+
static const struct camss_resources sdm660_resources = {
.version = CAMSS_660,
.csiphy_res = csiphy_res_660,
@@ -3865,6 +4012,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
+ { .compatible = "qcom,qcm2290-camss", .data = &qcm2290_resources },
{ .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v5 5/6] media: dt-bindings: Add qcom,qcm2290-camss
2025-07-04 8:15 [PATCH v5 0/6] media: qcom: camss: Add qcm2290 support Loic Poulain
` (3 preceding siblings ...)
2025-07-04 8:15 ` [PATCH v5 4/6] media: qcom: camss: add support for QCM2290 camss Loic Poulain
@ 2025-07-04 8:15 ` Loic Poulain
2025-07-05 9:01 ` Bryan O'Donoghue
2025-07-05 10:43 ` Krzysztof Kozlowski
2025-07-04 8:15 ` [PATCH v5 6/6] arm64: dts: qcom: qcm2290: Add CAMSS node Loic Poulain
5 siblings, 2 replies; 10+ messages in thread
From: Loic Poulain @ 2025-07-04 8:15 UTC (permalink / raw)
To: bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov,
Loic Poulain
Add bindings for qcom,qcm2290-camss in order to support the camera
subsystem found in the Qualcomm Robotics RB1 Platform (QRB2210).
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
.../bindings/media/qcom,qcm2290-camss.yaml | 243 ++++++++++++++++++
1 file changed, 243 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
new file mode 100644
index 000000000000..2824acd49d89
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
@@ -0,0 +1,243 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,qcm2290-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QCM2290 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Loic Poulain <loic.poulain@oss.qualcomm.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,qcm2290-camss
+
+ reg:
+ maxItems: 9
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csitpg0
+ - const: csitpg1
+ - const: top
+ - const: vfe0
+ - const: vfe1
+
+ clocks:
+ maxItems: 15
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: axi
+ - const: camnoc_nrt_axi
+ - const: camnoc_rt_axi
+ - const: csi0
+ - const: csi1
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: top_ahb
+ - const: vfe0
+ - const: vfe0_cphy_rx
+ - const: vfe1
+ - const: vfe1_cphy_rx
+
+ interrupts:
+ maxItems: 8
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csitpg0
+ - const: csitpg1
+ - const: vfe0
+ - const: vfe1
+
+ interconnects:
+ maxItems: 3
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+ - const: sf_mnoc
+
+ iommus:
+ maxItems: 4
+
+ power-domains:
+ items:
+ - description: GDSC CAMSS Block, Global Distributed Switch Controller.
+
+ vdd-csiphy-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSI PHYs.
+
+ vdd-csiphy-1p8-supply:
+ description:
+ Phandle to 1.8V regulator supply to CSI PHYs pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-3]+$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data from a CSIPHY.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - vdd-csiphy-1p2-supply
+ - vdd-csiphy-1p8-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
+ #include <dt-bindings/interconnect/qcom,rpm-icc.h>
+ #include <dt-bindings/interconnect/qcom,qcm2290.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: camss@5c6e000 {
+ compatible = "qcom,qcm2290-camss";
+
+ reg = <0x0 0x5c6e000 0x0 0x1000>,
+ <0x0 0x5c75000 0x0 0x1000>,
+ <0x0 0x5c52000 0x0 0x1000>,
+ <0x0 0x5c53000 0x0 0x1000>,
+ <0x0 0x5c66000 0x0 0x400>,
+ <0x0 0x5c68000 0x0 0x400>,
+ <0x0 0x5c11000 0x0 0x1000>,
+ <0x0 0x5c6f000 0x0 0x4000>,
+ <0x0 0x5c76000 0x0 0x4000>;
+ reg-names = "csid0",
+ "csid1",
+ "csiphy0",
+ "csiphy1",
+ "csitpg0",
+ "csitpg1",
+ "top",
+ "vfe0",
+ "vfe1";
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>,
+ <&gcc GCC_CAMSS_NRT_AXI_CLK>,
+ <&gcc GCC_CAMSS_RT_AXI_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
+ clock-names = "ahb",
+ "axi",
+ "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "csi0",
+ "csi1",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "top_ahb",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe1",
+ "vfe1_cphy_rx";
+
+ interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csiphy0",
+ "csiphy1",
+ "csitpg0",
+ "csitpg1",
+ "vfe0",
+ "vfe1";
+
+ interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
+ &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>,
+ <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+ <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc";
+
+ iommus = <&apps_smmu 0x400 0x0>,
+ <&apps_smmu 0x800 0x0>,
+ <&apps_smmu 0x820 0x0>,
+ <&apps_smmu 0x840 0x0>;
+
+ power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
+
+ vdd-csiphy-1p2-supply = <&pm4125_l5>;
+ vdd-csiphy-1p8-supply = <&pm4125_l13>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v5 5/6] media: dt-bindings: Add qcom,qcm2290-camss
2025-07-04 8:15 ` [PATCH v5 5/6] media: dt-bindings: Add qcom,qcm2290-camss Loic Poulain
@ 2025-07-05 9:01 ` Bryan O'Donoghue
2025-07-05 10:43 ` Krzysztof Kozlowski
1 sibling, 0 replies; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-07-05 9:01 UTC (permalink / raw)
To: Loic Poulain, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov
On 04/07/2025 09:15, Loic Poulain wrote:
> Add bindings for qcom,qcm2290-camss in order to support the camera
> subsystem found in the Qualcomm Robotics RB1 Platform (QRB2210).
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,qcm2290-camss.yaml | 243 ++++++++++++++++++
> 1 file changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
> new file mode 100644
> index 000000000000..2824acd49d89
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
> @@ -0,0 +1,243 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,qcm2290-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QCM2290 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Loic Poulain <loic.poulain@oss.qualcomm.com>
> +
> +description:
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
> +properties:
> + compatible:
> + const: qcom,qcm2290-camss
> +
> + reg:
> + maxItems: 9
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csitpg0
> + - const: csitpg1
> + - const: top
top should come first as its the main register bank in the list.
> + - const: vfe0
> + - const: vfe1
> +
> + clocks:
> + maxItems: 15
> +
> + clock-names:
> + items:
> + - const: ahb
> + - const: axi
> + - const: camnoc_nrt_axi
> + - const: camnoc_rt_axi
> + - const: csi0
> + - const: csi1
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: top_ahb
> + - const: vfe0
> + - const: vfe0_cphy_rx
> + - const: vfe1
> + - const: vfe1_cphy_rx
> +
> + interrupts:
> + maxItems: 8
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csitpg0
> + - const: csitpg1
> + - const: vfe0
> + - const: vfe1
> +
> + interconnects:
> + maxItems: 3
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> + - const: sf_mnoc
> +
> + iommus:
> + maxItems: 4
> +
> + power-domains:
> + items:
> + - description: GDSC CAMSS Block, Global Distributed Switch Controller.
> +
> + vdd-csiphy-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSI PHYs.
> +
> + vdd-csiphy-1p8-supply:
> + description:
> + Phandle to 1.8V regulator supply to CSI PHYs pll block.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-3]+$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> +
> + description:
> + Input port for receiving CSI data from a CSIPHY.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - vdd-csiphy-1p2-supply
> + - vdd-csiphy-1p8-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
> + #include <dt-bindings/interconnect/qcom,rpm-icc.h>
> + #include <dt-bindings/interconnect/qcom,qcm2290.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + camss: camss@5c6e000 {
> + compatible = "qcom,qcm2290-camss";
> +
> + reg = <0x0 0x5c6e000 0x0 0x1000>,
> + <0x0 0x5c75000 0x0 0x1000>,
> + <0x0 0x5c52000 0x0 0x1000>,
> + <0x0 0x5c53000 0x0 0x1000>,
> + <0x0 0x5c66000 0x0 0x400>,
> + <0x0 0x5c68000 0x0 0x400>,
> + <0x0 0x5c11000 0x0 0x1000>,
> + <0x0 0x5c6f000 0x0 0x4000>,
> + <0x0 0x5c76000 0x0 0x4000>;
> + reg-names = "csid0",
> + "csid1",
> + "csiphy0",
> + "csiphy1",
> + "csitpg0",
> + "csitpg1",
> + "top",
> + "vfe0",
> + "vfe1";
> +
> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> + <&gcc GCC_CAMSS_AXI_CLK>,
> + <&gcc GCC_CAMSS_NRT_AXI_CLK>,
> + <&gcc GCC_CAMSS_RT_AXI_CLK>,
> + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
> + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
> + <&gcc GCC_CAMSS_CPHY_0_CLK>,
> + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
> + <&gcc GCC_CAMSS_CPHY_1_CLK>,
> + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
> + <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> + <&gcc GCC_CAMSS_TFE_0_CLK>,
> + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
> + <&gcc GCC_CAMSS_TFE_1_CLK>,
> + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
> + clock-names = "ahb",
> + "axi",
> + "camnoc_nrt_axi",
> + "camnoc_rt_axi",
> + "csi0",
> + "csi1",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "top_ahb",
> + "vfe0",
> + "vfe0_cphy_rx",
> + "vfe1",
> + "vfe1_cphy_rx";
> +
> + interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csiphy0",
> + "csiphy1",
> + "csitpg0",
> + "csitpg1",
> + "vfe0",
> + "vfe1";
> +
> + interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
> + &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>,
> + <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
> + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
> + <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
> + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
> + interconnect-names = "ahb",
> + "hf_mnoc",
> + "sf_mnoc";
> +
> + iommus = <&apps_smmu 0x400 0x0>,
> + <&apps_smmu 0x800 0x0>,
> + <&apps_smmu 0x820 0x0>,
> + <&apps_smmu 0x840 0x0>;
> +
> + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
> +
> + vdd-csiphy-1p2-supply = <&pm4125_l5>;
> + vdd-csiphy-1p8-supply = <&pm4125_l13>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
Other than that LGTM.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v5 5/6] media: dt-bindings: Add qcom,qcm2290-camss
2025-07-04 8:15 ` [PATCH v5 5/6] media: dt-bindings: Add qcom,qcm2290-camss Loic Poulain
2025-07-05 9:01 ` Bryan O'Donoghue
@ 2025-07-05 10:43 ` Krzysztof Kozlowski
1 sibling, 0 replies; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-07-05 10:43 UTC (permalink / raw)
To: Loic Poulain, bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov
On 04/07/2025 10:15, Loic Poulain wrote:
> Add bindings for qcom,qcm2290-camss in order to support the camera
> subsystem found in the Qualcomm Robotics RB1 Platform (QRB2210).
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,qcm2290-camss.yaml | 243 ++++++++++++++++++
> 1 file changed, 243 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml
With Bryan comments fixed and *assuming you will do W=1 checks* afterwards:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v5 6/6] arm64: dts: qcom: qcm2290: Add CAMSS node
2025-07-04 8:15 [PATCH v5 0/6] media: qcom: camss: Add qcm2290 support Loic Poulain
` (4 preceding siblings ...)
2025-07-04 8:15 ` [PATCH v5 5/6] media: dt-bindings: Add qcom,qcm2290-camss Loic Poulain
@ 2025-07-04 8:15 ` Loic Poulain
5 siblings, 0 replies; 10+ messages in thread
From: Loic Poulain @ 2025-07-04 8:15 UTC (permalink / raw)
To: bryan.odonoghue, rfoss, konradybcio, krzk+dt, robh
Cc: linux-arm-msm, linux-media, devicetree, dmitry.baryshkov,
Loic Poulain, Konrad Dybcio
Add node for the QCM2290 camera subsystem.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/qcm2290.dtsi | 103 ++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
index f49ac1c1f8a3..fa24b77a31a7 100644
--- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
@@ -1628,6 +1628,109 @@ adreno_smmu: iommu@59a0000 {
#iommu-cells = <2>;
};
+ camss: camss@5c6e000 {
+ compatible = "qcom,qcm2290-camss";
+
+ reg = <0x0 0x5c6e000 0x0 0x1000>,
+ <0x0 0x5c75000 0x0 0x1000>,
+ <0x0 0x5c52000 0x0 0x1000>,
+ <0x0 0x5c53000 0x0 0x1000>,
+ <0x0 0x5c66000 0x0 0x400>,
+ <0x0 0x5c68000 0x0 0x400>,
+ <0x0 0x5c11000 0x0 0x1000>,
+ <0x0 0x5c6f000 0x0 0x4000>,
+ <0x0 0x5c76000 0x0 0x4000>;
+ reg-names = "csid0",
+ "csid1",
+ "csiphy0",
+ "csiphy1",
+ "csitpg0",
+ "csitpg1",
+ "top",
+ "vfe0",
+ "vfe1";
+
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>,
+ <&gcc GCC_CAMSS_NRT_AXI_CLK>,
+ <&gcc GCC_CAMSS_RT_AXI_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK> ;
+ clock-names = "ahb",
+ "axi",
+ "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "csi0",
+ "csi1",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "top_ahb",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe1",
+ "vfe1_cphy_rx";
+
+ interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csiphy0",
+ "csiphy1",
+ "csitpg0",
+ "csitpg1",
+ "vfe0",
+ "vfe1";
+
+ interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
+ &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>,
+ <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
+ <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc";
+
+ iommus = <&apps_smmu 0x400 0x0>,
+ <&apps_smmu 0x800 0x0>,
+ <&apps_smmu 0x820 0x0>,
+ <&apps_smmu 0x840 0x0>;
+
+ power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
mdss: display-subsystem@5e00000 {
compatible = "qcom,qcm2290-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread