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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b7327a48bc7sm321134966b.71.2025.11.12.03.20.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Nov 2025 03:20:31 -0800 (PST) Message-ID: <4e9d15cd-1ef2-464c-b421-f8a333c53825@oss.qualcomm.com> Date: Wed, 12 Nov 2025 12:20:29 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] power: reset: qcom-pon: Add support for WARM reset To: Loic Poulain Cc: krzk+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, conor+dt@kernel.org, sre@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org References: <20251103182006.1158383-1-loic.poulain@oss.qualcomm.com> <20251103182006.1158383-3-loic.poulain@oss.qualcomm.com> <740b9e7c-59bc-4a35-a268-526d92db372c@oss.qualcomm.com> <6daf722b-6b1b-4c91-b108-74793d930319@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 5fUD9Xian9s3Rzdn9zViksHQdDvKLFjJ X-Authority-Analysis: v=2.4 cv=eO4eTXp1 c=1 sm=1 tr=0 ts=69146d80 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=NEAV23lmAAAA:8 a=EUspDBNiAAAA:8 a=oAzUKsySGAh57qx-K-8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDA5MSBTYWx0ZWRfXz0baQ+3qemYj jCEPGWZ9u7H1clXuO5uuuIrhTX5fmPabseZjqSHlgiMLdPF2ynwo2Qvw/DOHUEocqHijcsHrXru /+VKVOaJa/15TBKRTFA1+s4bxisifU90wTgKqCHrEFRGKF5Y+dwMbYpbOnRdWhC8H2fUcYR4raB ijC6DORp9x4uhTJtDK/aSPDWq63tWzcgrT0OrY0mSYg10V5z0XolX7PCC2IOd+b81Up0yL5sePh 29WDVtjZu14734H9jRsl+RO2Mh9+LuirD6CTVU8ZUWZJn8k78tx7m/IS87L38JgdYvT5/gUJYQE 9urAhiOClirKUvxXtItU5TwRBPvSCk8BBLFST+MOvTT6fvZAEC96wWLwZq4Pg3Sh3oKUl3PzG2x kXuL/AD7LrTgo/VAShi8qMaiOk9Tzg== X-Proofpoint-ORIG-GUID: 5fUD9Xian9s3Rzdn9zViksHQdDvKLFjJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120091 On 11/12/25 12:16 PM, Loic Poulain wrote: > Hi Konrad, > > On Thu, Nov 6, 2025 at 1:50 PM Konrad Dybcio > wrote: >> >> On 11/5/25 10:44 PM, Loic Poulain wrote: >>> Hi Konrad, >>> >>> On Tue, Nov 4, 2025 at 4:20 PM Konrad Dybcio >>> wrote: >>>> >>>> On 11/4/25 4:01 PM, Loic Poulain wrote: >>>>> Hi Konrad, Krzysztof, >>>>> >>>>> On Tue, Nov 4, 2025 at 12:50 PM Konrad Dybcio >>>>> wrote: >>>>>> >>>>>> On 11/3/25 7:20 PM, Loic Poulain wrote: >>>>>>> This mechanism can be used when firmware lacks proper warm-reset handling, >>>>>>> for example, when the PSCI SYSTEM_RESET2 function is not implemented. >>>>>>> It enables the warm reset functionality via the PMIC. >>>>>>> >>>>>>> This fallback is only enabled if qcom,warm-reset property is present. >>>>>>> >>>>>>> Signed-off-by: Loic Poulain >>>>>>> --- >>>>>>> drivers/power/reset/qcom-pon.c | 47 ++++++++++++++++++++++++++++++++++ >>>>>>> 1 file changed, 47 insertions(+) >>>>>>> >>>>>>> diff --git a/drivers/power/reset/qcom-pon.c b/drivers/power/reset/qcom-pon.c >>>>>>> index 7e108982a582..684e9fe9987d 100644 >>>>>>> --- a/drivers/power/reset/qcom-pon.c >>>>>>> +++ b/drivers/power/reset/qcom-pon.c >>>>>>> @@ -19,12 +19,20 @@ >>>>>>> >>>>>>> #define NO_REASON_SHIFT 0 >>>>>>> >>>>>>> +#define PON_SW_RESET_S2_CTL 0x62 >>>>>>> +#define PON_SW_RESET_S2_CTL_WARM_RST 0x01 >>>>>>> +#define PON_SW_RESET_S2_CTL2 0x63 >>>>>>> +#define PON_SW_RESET_S2_CTL2_RST_EN BIT(7) >>>>>>> +#define PON_SW_RESET_GO 0x64 >>>>>>> +#define PON_SW_RESET_GO_MAGIC 0xa5 >>>>>> >>>>>> Going back to msm8974 where the SPMI arbiter first showed up, these >>>>>> values are all seemingly valid, so I think we can drop the dt property. >>>>>> The restart reasons are set in stone too, and you can find more of them >>>>>> in the register description. >>>>> >>>>> Yes, but this should only apply when the platform firmware does not >>>>> support warm reset via PSCI, right? >>>>> Making it unconditional would override the PSCI implementation even >>>>> when warm reset is supported. >>>>> >>>>> The point is that psci_sys_reset() executes a cold reset if warm >>>>> reset isn’t available. Therefore, our PMIC reboot notifier must have a >>>>> higher priority than the PSCI handler. >>>>> >>>>> So maybe the alternative could be to introduce an additional reboot >>>>> handler in psci, with the lowest priority, so that warm reset can have >>>>> a chance to run either from the psci main reboot handler or from the >>>>> PMIC reboot handler before falling back to cold reset? >>>>> [PSCI-handler]->[other-handlers]->[PSCI-cold-reset-fallback-handler] >>>> >>>> This seems like a common enough problem, perhaps the framework could >>>> accept EOPNOTSUPP or similar and try to delegate further, coming back >>>> with a normal restart or so, if unsupported. Trying to make a special >>>> contract between qcom-pon and psci silently will be very fragile >>>> otherwise. >>> >>> I tested the following, as described above: >>> https://github.com/loicpoulain/linux/commit/5c34ea54e1a21ff1192c3c341877b24eff5f80b4 >>> The only special 'contract' is the handler priority. >>> If you can elaborate on another/better approach, that would be helpful. >> >> Thinking about it again, it'd be difficult to grab some sort of a handle >> to the ""parent"" reboot mode, so what you propose here is good >> >>>>>> That said, we're circumventing PS_HOLD this way - is that intended? >>>>> >>>>> Well, we don’t have direct control over PS_HOLD since it’s managed by >>>>> the firmware in our case. That’s why I considered using the PMIC >>>>> software reset as an effective way to achieve this warm reset. >>>> >>>> Hm, so is there no longer a way to assert it by writing to PMIC >>>> registers? >>> >>> PS_HOLD is a SoC signal, and we can maybe assert it via the >>> MPM_PS_HOLD register through the msm-poweroff driver if needed (well, >>> if access is allowed from a non-secure world). >>> However, this would also require coordination with the PMIC driver to >>> select the correct PS_HOLD action (shutdown, cold reset, warm reset). >>> For that reason, I’d prefer to keep PS_HOLD based logic abstracted by PSCI. >>> Using the SW_RST PMIC register allows us to perform a reset without >>> additional signal handling. >> >> Yeah of course we should use PSCI where functional and available >> >> I think PS_HOLD used to be fully manual on old (msm-3.10) platforms >> through PMIC registers. I see that e.g. msm-4.19 has an SCM call to >> (de)assert it. There's also a "halt PMIC arbiter" call. >> >> (via drivers/power/reset/msm-poweroff.c) > > Yes I could try the SCM call to deassert PS_HOLD, is it something we > should prefer over PMIC soft reset? > Asking because the implication would be a more complex solution > (though not yet tested): > - Adding reboot mode support in qcom-scm to activate ELD mode > - Adding reset-notifier in pmic driver to modify PS_HOLD action to warm-reset > - Adding reset-notifier in qcom,scm (of lower priority than PMIC) > doing the actual SCM ps-hold deassert > - Ensuring that PSCI is still used for cold-reset and warm-reset when > supported... My answer is unfortunately "I don't know". We should loop in some PMIC folks that would know the difference Konrad