[PATCH 0/7] Add SC7280 audioreach device tree nodes.

[PATCH 0/7] Add SC7280 audioreach device tree nodes.

[Srinivasa Rao Mandadapu]

Add SC7280 audioreach device tree nodes and extract audio specific
dtsi nodes and add them in new file.

Srinivasa Rao Mandadapu (7):
  arm64: dts: qcom: sc7280: Extract audio nodes from common idp dtsi
    file
  arm64: dts: qcom: sc7280: audioreach: Add sound node
  arm64: dts: qcom: sc7280: audioreach: Add lpass pil node
  arm64: dts: qcom: sc7280: audioreach: Update lpasscc reg property
  arm64: dts: qcom: sc7280: audioreach: Add CGCR reset property
  arm64: dts: qcom: sc7280: audioreach: Update VA/RX/TX macro clock
    nodes
  arm64: dts: qcom: sc7280: audioreach: Disable legacy path clock nodes

 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi     | 242 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts         |  24 +-
 .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi  | 283 +++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi           | 230 -----------------
 arch/arm64/boot/dts/qcom/sc7280-idp2.dts           |   1 +
 5 files changed, 527 insertions(+), 253 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi

-- 
2.7.4

[PATCH 1/7] arm64: dts: qcom: sc7280: Extract audio nodes from common idp dtsi file

[Srinivasa Rao Mandadapu]

Split common idp dtsi file into audio specific dtsi and common
idp dtsi file.

It is required to isolate idp and crd-rev3 platform device tree nodes
and convert crd-rev3 platform device tree nodes into audioreach specific
device tree nodes.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi | 242 +++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts     |   1 +
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi       | 230 -----------------------
 arch/arm64/boot/dts/qcom/sc7280-idp2.dts       |   1 +
 4 files changed, 244 insertions(+), 230 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
new file mode 100644
index 0000000..8c9e667
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 Audio IDP board device tree source (common between SKU1 and SKU2)
+ *
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ */
+
+/{
+   /* BOARD-SPECIFIC TOP LEVEL NODES */
+	sound: sound {
+		compatible = "google,sc7280-herobrine";
+		model = "sc7280-wcd938x-max98360a-1mic";
+
+		audio-routing =
+			   "IN1_HPHL", "HPHL_OUT",
+			   "IN2_HPHR", "HPHR_OUT",
+			   "AMIC1", "MIC BIAS1",
+			   "AMIC2", "MIC BIAS2",
+			   "VA DMIC0", "MIC BIAS3",
+			   "VA DMIC1", "MIC BIAS3",
+			   "VA DMIC2", "MIC BIAS1",
+			   "VA DMIC3", "MIC BIAS1",
+			   "TX SWR_ADC0", "ADC1_OUTPUT",
+			   "TX SWR_ADC1", "ADC2_OUTPUT",
+			   "TX SWR_ADC2", "ADC3_OUTPUT",
+			   "TX SWR_DMIC0", "DMIC1_OUTPUT",
+			   "TX SWR_DMIC1", "DMIC2_OUTPUT",
+			   "TX SWR_DMIC2", "DMIC3_OUTPUT",
+			   "TX SWR_DMIC3", "DMIC4_OUTPUT",
+			   "TX SWR_DMIC4", "DMIC5_OUTPUT",
+			   "TX SWR_DMIC5", "DMIC6_OUTPUT",
+			   "TX SWR_DMIC6", "DMIC7_OUTPUT",
+			   "TX SWR_DMIC7", "DMIC8_OUTPUT";
+
+		qcom,msm-mbhc-hphl-swh = <1>;
+		qcom,msm-mbhc-gnd-swh = <1>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#sound-dai-cells = <0>;
+
+		dai-link@0 {
+			link-name = "MAX98360A";
+			reg = <0>;
+
+			cpu {
+				sound-dai = <&lpass_cpu MI2S_SECONDARY>;
+			};
+
+			codec {
+			   sound-dai = <&max98360a>;
+			};
+		};
+
+		dai-link@1 {
+			link-name = "DisplayPort";
+			reg = <1>;
+
+			cpu {
+				sound-dai = <&lpass_cpu LPASS_DP_RX>;
+			};
+
+			codec {
+				sound-dai = <&mdss_dp>;
+			};
+		};
+
+		dai-link@2 {
+			link-name = "WCD9385 Playback";
+			reg = <2>;
+
+			cpu {
+				sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
+			};
+
+			codec {
+				sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+			};
+		};
+
+		dai-link@3 {
+			link-name = "WCD9385 Capture";
+			reg = <3>;
+
+			cpu {
+				sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
+			};
+
+			codec {
+				sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+			};
+		};
+
+		dai-link@4 {
+			link-name = "DMIC";
+			reg = <4>;
+
+			cpu {
+				sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_va_macro 0>;
+			};
+		};
+	};
+
+	wcd9385: audio-codec-1 {
+		compatible = "qcom,wcd9385-codec";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&wcd_reset_n>;
+		pinctrl-1 = <&wcd_reset_n_sleep>;
+
+		reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		vdd-rxtx-supply = <&vreg_l18b_1p8>;
+		vdd-io-supply = <&vreg_l18b_1p8>;
+		vdd-buck-supply = <&vreg_l17b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
+							  500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		#sound-dai-cells = <1>;
+	};
+
+};
+
+&lpass_cpu {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
+
+	dai-link@1 {
+		reg = <MI2S_SECONDARY>;
+		qcom,playback-sd-lines = <0>;
+	};
+
+	dai-link@5 {
+		reg = <LPASS_DP_RX>;
+	};
+
+	dai-link@6 {
+		reg = <LPASS_CDC_DMA_RX0>;
+	};
+
+	dai-link@19 {
+		reg = <LPASS_CDC_DMA_TX3>;
+	};
+
+	dai-link@25 {
+		reg = <LPASS_CDC_DMA_VA_TX0>;
+	};
+};
+
+&lpass_rx_macro {
+	status = "okay";
+};
+
+&lpass_tx_macro {
+	status = "okay";
+};
+
+&lpass_va_macro {
+	status = "okay";
+	vdd-micb-supply = <&vreg_bob>;
+};
+
+&swr0 {
+	status = "okay";
+
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		#sound-dai-cells = <1>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		#sound-dai-cells = <1>;
+		qcom,tx-port-mapping = <1 2 3 4>;
+	};
+};
+
+&lpass_dmic01_clk {
+	drive-strength = <8>;
+	bias-disable;
+};
+
+&lpass_dmic01_data {
+	   bias-pull-down;
+};
+
+&lpass_dmic23_clk {
+	drive-strength = <8>;
+	bias-disable;
+};
+
+&lpass_dmic23_data {
+	bias-pull-down;
+};
+
+&lpass_rx_swr_clk {
+	drive-strength = <2>;
+	slew-rate = <1>;
+	bias-disable;
+};
+
+&lpass_rx_swr_data {
+	drive-strength = <2>;
+	slew-rate = <1>;
+	bias-bus-hold;
+};
+
+&lpass_tx_swr_clk {
+	drive-strength = <2>;
+	slew-rate = <1>;
+	bias-disable;
+};
+
+&lpass_tx_swr_data {
+	drive-strength = <2>;
+	slew-rate = <1>;
+	bias-bus-hold;
+};
+
diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
index 1185141..b024626 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "sc7280-idp.dtsi"
+#include "sc7280-audio-idp.dtsi"
 #include "sc7280-idp-ec-h1.dtsi"
 
 / {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index f7efb99..7e35867 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -29,34 +29,6 @@
 		#sound-dai-cells = <0>;
 	};
 
-	wcd9385: audio-codec-1 {
-		compatible = "qcom,wcd9385-codec";
-		pinctrl-names = "default", "sleep";
-		pinctrl-0 = <&wcd_reset_n>;
-		pinctrl-1 = <&wcd_reset_n_sleep>;
-
-		reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
-
-		qcom,rx-device = <&wcd_rx>;
-		qcom,tx-device = <&wcd_tx>;
-
-		vdd-rxtx-supply = <&vreg_l18b_1p8>;
-		vdd-io-supply = <&vreg_l18b_1p8>;
-		vdd-buck-supply = <&vreg_l17b_1p8>;
-		vdd-mic-bias-supply = <&vreg_bob>;
-
-		qcom,micbias1-microvolt = <1800000>;
-		qcom,micbias2-microvolt = <1800000>;
-		qcom,micbias3-microvolt = <1800000>;
-		qcom,micbias4-microvolt = <1800000>;
-
-		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
-							  500000 500000 500000>;
-		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
-		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
-		#sound-dai-cells = <1>;
-	};
-
 	gpio-keys {
 		compatible = "gpio-keys";
 		label = "gpio-keys";
@@ -87,103 +59,6 @@
 		pinctrl-0 = <&nvme_pwren>;
 	};
 
-	sound: sound {
-		compatible = "google,sc7280-herobrine";
-		model = "sc7280-wcd938x-max98360a-1mic";
-
-		audio-routing =
-			"IN1_HPHL", "HPHL_OUT",
-			"IN2_HPHR", "HPHR_OUT",
-			"AMIC1", "MIC BIAS1",
-			"AMIC2", "MIC BIAS2",
-			"VA DMIC0", "MIC BIAS3",
-			"VA DMIC1", "MIC BIAS3",
-			"VA DMIC2", "MIC BIAS1",
-			"VA DMIC3", "MIC BIAS1",
-			"TX SWR_ADC0", "ADC1_OUTPUT",
-			"TX SWR_ADC1", "ADC2_OUTPUT",
-			"TX SWR_ADC2", "ADC3_OUTPUT",
-			"TX SWR_DMIC0", "DMIC1_OUTPUT",
-			"TX SWR_DMIC1", "DMIC2_OUTPUT",
-			"TX SWR_DMIC2", "DMIC3_OUTPUT",
-			"TX SWR_DMIC3", "DMIC4_OUTPUT",
-			"TX SWR_DMIC4", "DMIC5_OUTPUT",
-			"TX SWR_DMIC5", "DMIC6_OUTPUT",
-			"TX SWR_DMIC6", "DMIC7_OUTPUT",
-			"TX SWR_DMIC7", "DMIC8_OUTPUT";
-
-		qcom,msm-mbhc-hphl-swh = <1>;
-		qcom,msm-mbhc-gnd-swh = <1>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-		#sound-dai-cells = <0>;
-
-		dai-link@0 {
-			link-name = "MAX98360A";
-			reg = <0>;
-
-			cpu {
-				sound-dai = <&lpass_cpu MI2S_SECONDARY>;
-			};
-
-			codec {
-				sound-dai = <&max98360a>;
-			};
-		};
-
-		dai-link@1 {
-			link-name = "DisplayPort";
-			reg = <1>;
-
-			cpu {
-				sound-dai = <&lpass_cpu LPASS_DP_RX>;
-			};
-
-			codec {
-				sound-dai = <&mdss_dp>;
-			};
-		};
-
-		dai-link@2 {
-			link-name = "WCD9385 Playback";
-			reg = <2>;
-
-			cpu {
-				sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
-			};
-
-			codec {
-				sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>;
-			};
-		};
-
-		dai-link@3 {
-			link-name = "WCD9385 Capture";
-			reg = <3>;
-
-			cpu {
-				sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
-			};
-
-			codec {
-				sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>;
-			};
-		};
-
-		dai-link@4 {
-			link-name = "DMIC";
-			reg = <4>;
-
-			cpu {
-				sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
-			};
-
-			codec {
-				sound-dai = <&lpass_va_macro 0>;
-			};
-		};
-	};
 };
 
 &apps_rsc {
@@ -381,47 +256,6 @@
 	modem-init;
 };
 
-&lpass_cpu {
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
-
-	dai-link@1 {
-		reg = <MI2S_SECONDARY>;
-		qcom,playback-sd-lines = <0>;
-	};
-
-	dai-link@5 {
-		reg = <LPASS_DP_RX>;
-	};
-
-	dai-link@6 {
-		reg = <LPASS_CDC_DMA_RX0>;
-	};
-
-	dai-link@19 {
-		reg = <LPASS_CDC_DMA_TX3>;
-	};
-
-	dai-link@25 {
-		reg = <LPASS_CDC_DMA_VA_TX0>;
-	};
-};
-
-&lpass_rx_macro {
-	status = "okay";
-};
-
-&lpass_tx_macro {
-	status = "okay";
-};
-
-&lpass_va_macro {
-	status = "okay";
-	vdd-micb-supply = <&vreg_bob>;
-};
-
 &pcie1 {
 	status = "okay";
 	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
@@ -482,28 +316,6 @@
 	cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
 };
 
-&swr0 {
-	status = "okay";
-
-	wcd_rx: codec@0,4 {
-		compatible = "sdw20217010d00";
-		reg = <0 4>;
-		#sound-dai-cells = <1>;
-		qcom,rx-port-mapping = <1 2 3 4 5>;
-	};
-};
-
-&swr1 {
-	status = "okay";
-
-	wcd_tx: codec@0,3 {
-		compatible = "sdw20217010d00";
-		reg = <0 3>;
-		#sound-dai-cells = <1>;
-		qcom,tx-port-mapping = <1 2 3 4>;
-	};
-};
-
 &uart5 {
 	compatible = "qcom,geni-debug-uart";
 	status = "okay";
@@ -571,48 +383,6 @@
 	bias-disable;
 };
 
-&lpass_dmic01_clk {
-	drive-strength = <8>;
-	bias-disable;
-};
-
-&lpass_dmic01_data {
-	bias-pull-down;
-};
-
-&lpass_dmic23_clk {
-	drive-strength = <8>;
-	bias-disable;
-};
-
-&lpass_dmic23_data {
-	bias-pull-down;
-};
-
-&lpass_rx_swr_clk {
-	drive-strength = <2>;
-	slew-rate = <1>;
-	bias-disable;
-};
-
-&lpass_rx_swr_data {
-	drive-strength = <2>;
-	slew-rate = <1>;
-	bias-bus-hold;
-};
-
-&lpass_tx_swr_clk {
-	drive-strength = <2>;
-	slew-rate = <1>;
-	bias-disable;
-};
-
-&lpass_tx_swr_data {
-	drive-strength = <2>;
-	slew-rate = <1>;
-	bias-bus-hold;
-};
-
 &mi2s1_data0 {
 	drive-strength = <6>;
 	bias-disable;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
index d4f7cab..bc1a1a8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "sc7280-idp.dtsi"
+#include "sc7280-audio-idp.dtsi"
 #include "sc7280-idp-ec-h1.dtsi"
 
 / {
-- 
2.7.4

[PATCH 2/7] arm64: dts: qcom: sc7280: audioreach: Add sound node

[Srinivasa Rao Mandadapu]

Add sound node for sc7280 based audioreach platforms.

Include audioreach dtsi into crd-rev3 platform specific dts file.
Also remove phandle to sound node, as audio routing is same as
audioreach specific dtsi file.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts         |  25 +----
 .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi  | 112 +++++++++++++++++++++
 2 files changed, 113 insertions(+), 24 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi

diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
index b024626..aea8cbd 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
@@ -8,7 +8,7 @@
 /dts-v1/;
 
 #include "sc7280-idp.dtsi"
-#include "sc7280-audio-idp.dtsi"
+#include "sc7280-herobrine-audioreach-wcd9385.dtsi"
 #include "sc7280-idp-ec-h1.dtsi"
 
 / {
@@ -88,29 +88,6 @@ ap_ts_pen_1v8: &i2c13 {
 	pins = "gpio51";
 };
 
-&sound {
-	audio-routing =
-		"IN1_HPHL", "HPHL_OUT",
-		"IN2_HPHR", "HPHR_OUT",
-		"AMIC1", "MIC BIAS1",
-		"AMIC2", "MIC BIAS2",
-		"VA DMIC0", "MIC BIAS1",
-		"VA DMIC1", "MIC BIAS1",
-		"VA DMIC2", "MIC BIAS3",
-		"VA DMIC3", "MIC BIAS3",
-		"TX SWR_ADC0", "ADC1_OUTPUT",
-		"TX SWR_ADC1", "ADC2_OUTPUT",
-		"TX SWR_ADC2", "ADC3_OUTPUT",
-		"TX SWR_DMIC0", "DMIC1_OUTPUT",
-		"TX SWR_DMIC1", "DMIC2_OUTPUT",
-		"TX SWR_DMIC2", "DMIC3_OUTPUT",
-		"TX SWR_DMIC3", "DMIC4_OUTPUT",
-		"TX SWR_DMIC4", "DMIC5_OUTPUT",
-		"TX SWR_DMIC5", "DMIC6_OUTPUT",
-		"TX SWR_DMIC6", "DMIC7_OUTPUT",
-		"TX SWR_DMIC7", "DMIC8_OUTPUT";
-};
-
 &wcd9385 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
new file mode 100644
index 0000000..1eac94e1
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 device tree source for boards using Max98360 and wcd9385 codec
+ * along with ADSP
+ *
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/clock/qcom,lpass-sc7280.h>
+
+/{
+	/* BOARD-SPECIFIC TOP LEVEL NODES */
+	sound: sound {
+		compatible = "google,sc7280-herobrine";
+		model = "SC7280-AUDIOREACH";
+		status = "okay";
+		adsp-mode;
+		audio-routing =
+		   "IN1_HPHL", "HPHL_OUT",
+		   "IN2_HPHR", "HPHR_OUT",
+		   "AMIC1", "MIC BIAS1",
+		   "AMIC2", "MIC BIAS2",
+		   "VA DMIC0", "MIC BIAS1",
+		   "VA DMIC1", "MIC BIAS1",
+		   "VA DMIC2", "MIC BIAS3",
+		   "VA DMIC3", "MIC BIAS3",
+		   "TX SWR_ADC0", "ADC1_OUTPUT",
+		   "TX SWR_ADC1", "ADC2_OUTPUT",
+		   "TX SWR_ADC2", "ADC3_OUTPUT",
+		   "TX SWR_DMIC0", "DMIC1_OUTPUT",
+		   "TX SWR_DMIC1", "DMIC2_OUTPUT",
+		   "TX SWR_DMIC2", "DMIC3_OUTPUT",
+		   "TX SWR_DMIC3", "DMIC4_OUTPUT",
+		   "TX SWR_DMIC4", "DMIC5_OUTPUT",
+		   "TX SWR_DMIC5", "DMIC6_OUTPUT",
+		   "TX SWR_DMIC6", "DMIC7_OUTPUT",
+		   "TX SWR_DMIC7", "DMIC8_OUTPUT";
+
+		qcom,msm-mbhc-hphl-swh = <1>;
+		qcom,msm-mbhc-gnd-swh = <1>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#sound-dai-cells = <0>;
+
+		dai-link@0 {
+			link-name = "WCD9385 Playback";
+			reg = <0>;
+
+			cpu {
+				sound-dai = <&q6apmbedai  RX_CODEC_DMA_RX_0>;
+			};
+			codec {
+				sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+			};
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		dai-link@1 {
+			link-name = "WCD9385 Capture";
+			reg = <1>;
+
+			cpu {
+				sound-dai = <&q6apmbedai  TX_CODEC_DMA_TX_3>;
+			};
+			codec {
+				sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+			};
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		dai-link@2 {
+			link-name = "MAX98360A";
+			reg = <3>;
+
+			cpu {
+				sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>;
+			};
+
+			codec {
+				sound-dai =	 <&max98360a>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		dai-link@3 {
+			link-name = "DMIC";
+			reg = <4>;
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_va_macro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+};
-- 
2.7.4

[PATCH 3/7] arm64: dts: qcom: sc7280: audioreach: Add lpass pil node

[Srinivasa Rao Mandadapu]

Add lpass pil node for sc7280 based audioreach platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
This patch depends on:
    -- https://lore.kernel.org/linux-remoteproc/6e0590af-0bd1-cbef-c573-fa62b5bc9e63@quicinc.com/

 .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi  | 99 ++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
index 1eac94e1..0ce8755 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
@@ -110,3 +110,102 @@
 		};
 	};
 };
+
+&soc {
+	qcom,lpass@3000000 {
+		compatible = "qcom,sc7280-adsp-pil";
+		reg = <0 0x03000000 0 0x5000>,
+			<0 0x0355b000 0 0x10>;
+
+		reg-names = "qdsp6ss_base",
+			"lpass_efuse";
+
+		interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+					<&adsp_smp2p_in 0 0>,
+					<&adsp_smp2p_in 1 0>,
+					<&adsp_smp2p_in 2 0>,
+					<&adsp_smp2p_in 3 0>,
+					<&adsp_smp2p_in 7 0>;
+
+		interrupt-names = "wdog", "fatal", "ready",
+			"handover", "stop-ack",  "shutdown-ack";
+		qcom,qmp = <&aoss_qmp>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_CFG_NOC_LPASS_CLK>,
+			<&lpasscc LPASS_QDSP6SS_XO_CLK>,
+			<&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
+			<&lpasscc LPASS_QDSP6SS_CORE_CLK>;
+
+		clock-names = "xo", "gcc_cfg_noc_lpass",
+				"lpass_qdsp6ss_xo",
+				"lpass_qdsp6ss_sleep",
+				"lpass_qdsp6ss_core";
+
+		iommus = <&apps_smmu 0x1800 0x0>;
+
+		power-domains =	<&rpmhpd SC7280_LCX>;
+		power-domain-names = "lcx";
+		required-opps = <&rpmhpd_opp_nom>;
+
+		resets = <&aoss_reset AOSS_CC_LPASS_RESTART>,
+			<&pdc_reset PDC_AUDIO_SYNC_RESET>;
+
+		reset-names = "cc_lpass", "pdc_sync";
+
+		qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
+
+		memory-region = <&adsp_mem>;
+
+		status = "okay";
+
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink-edge {
+			interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP
+						IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc IPCC_CLIENT_LPASS
+					IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+			label = "lpass";
+			qcom,remote-pid = <2>;
+
+			gpr {
+				compatible = "qcom,gpr";
+				qcom,glink-channels = "adsp_apps";
+				qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				qcom,intents = <512 20>;
+
+				q6apm: q6apm {
+					reg = <GPR_APM_MODULE_IID>;
+					compatible = "qcom,q6apm";
+					#sound-dai-cells = <0>;
+					q6apmdai: dais {
+						compatible = "qcom,q6apm-dais";
+						#sound-dai-cells = <1>;
+						iommus = <&apps_smmu 0x1801 0x0>;
+					};
+
+					q6apmbedai: bedais {
+						compatible = "qcom,q6apm-lpass-dais";
+						#sound-dai-cells = <1>;
+					};
+				};
+
+				q6prm: q6prm {
+					reg = <GPR_PRM_MODULE_IID>;
+					compatible = "qcom,q6prm";
+					#clock-cells = <2>;
+					q6prmcc: cc {
+						compatible = "qcom,q6prm-lpass-clocks";
+						#clock-cells = <2>;
+					};
+				};
+			};
+		};
+	};
+};
-- 
2.7.4

[PATCH 4/7] arm64: dts: qcom: sc7280: audioreach: Update lpasscc reg property

[Srinivasa Rao Mandadapu]

Update lpasscc register mapping for avoiding memory regions conflict with
ADSP pil node.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
index 0ce8755..a750f05 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
@@ -111,6 +111,14 @@
 	};
 };
 
+&lpasscc {
+	reg = <0 0x03c04000 0 0x4>,
+		<0 0x032a9000 0 0x1000>;
+	reg-names = "top_cc", "reset-cgcr";
+	#reset-cells = <1>;
+	status = "okay";
+};
+
 &soc {
 	qcom,lpass@3000000 {
 		compatible = "qcom,sc7280-adsp-pil";
-- 
2.7.4

[PATCH 5/7] arm64: dts: qcom: sc7280: audioreach: Add CGCR reset property

[Srinivasa Rao Mandadapu]

Add CGCR register reset property for both RX and TX soundwire
slave devices.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
This patch depends on:
    -- https://lore.kernel.org/linux-clk/1671618061-6329-1-git-send-email-quic_srivasam@quicinc.com/

 .../arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
index a750f05..ce5d69e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
@@ -217,3 +217,12 @@
 		};
 	};
 };
+
+&swr0 {
+	resets = <&lpasscc LPASS_AUDIO_SWR_RX_CGCR>;
+};
+
+&swr1 {
+	resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
+};
+
-- 
2.7.4

[PATCH 6/7] arm64: dts: qcom: sc7280: audioreach: Update VA/RX/TX macro clock nodes

[Srinivasa Rao Mandadapu]

Update VA, RX and TX macro and lpass_tlmm clock properties and
enable them.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi  | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
index ce5d69e..a0061ef 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
@@ -119,6 +119,49 @@
 	status = "okay";
 };
 
+&lpass_tlmm {
+	clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+
+	clock-names = "core", "audio";
+	reg = <0 0x033c0000 0x0 0x20000>,
+	      <0 0x03550000 0x0 0xa100>;
+};
+
+&lpass_va_macro {
+	clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+
+	clock-names = "mclk", "macro", "dcodec";
+	power-domain-names = "null";
+	status = "okay";
+};
+
+&lpass_rx_macro {
+	clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&lpass_va_macro>;
+
+	clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+	power-domain-names = "null";
+	status = "okay";
+};
+
+&lpass_tx_macro {
+	clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+		 <&lpass_va_macro>;
+
+	clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
+	power-domain-names = "null";
+	status = "okay";
+};
+
 &soc {
 	qcom,lpass@3000000 {
 		compatible = "qcom,sc7280-adsp-pil";
-- 
2.7.4

[PATCH 7/7] arm64: dts: qcom: sc7280: audioreach: Disable legacy path clock nodes

[Srinivasa Rao Mandadapu]

Disable legacy path clock nodes to avoid conflicts with audioreach
clock node.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 .../boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
index a0061ef..dce0114 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
@@ -162,6 +162,18 @@
 	status = "okay";
 };
 
+&lpass_core {
+	status = "disabled";
+};
+
+&lpass_aon {
+	status = "disabled";
+};
+
+&lpass_audiocc {
+	status = "disabled";
+};
+
 &soc {
 	qcom,lpass@3000000 {
 		compatible = "qcom,sc7280-adsp-pil";
-- 
2.7.4

Re: [PATCH 1/7] arm64: dts: qcom: sc7280: Extract audio nodes from common idp dtsi file

[Krzysztof Kozlowski]

On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Split common idp dtsi file into audio specific dtsi and common
> idp dtsi file.
> 
> It is required to isolate idp and crd-rev3 platform device tree nodes
> and convert crd-rev3 platform device tree nodes into audioreach specific
> device tree nodes.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi | 242 +++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts     |   1 +
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi       | 230 -----------------------
>  arch/arm64/boot/dts/qcom/sc7280-idp2.dts       |   1 +
>  4 files changed, 244 insertions(+), 230 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
> new file mode 100644
> index 0000000..8c9e667
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7280-audio-idp.dtsi
> @@ -0,0 +1,242 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * sc7280 Audio IDP board device tree source (common between SKU1 and SKU2)
> + *
> + * Copyright (c) 2022, The Linux Foundation. All rights reserved.
> + */
> +

Mising includes. Each file is responsible for its own includes and must
not rely on others to include something.

> +/{
> +   /* BOARD-SPECIFIC TOP LEVEL NODES */

Wrong indentation.

> +	sound: sound {
> +		compatible = "google,sc7280-herobrine";
> +		model = "sc7280-wcd938x-max98360a-1mic";
> +
> +		audio-routing =
> +			   "IN1_HPHL", "HPHL_OUT",
> +			   "IN2_HPHR", "HPHR_OUT",
> +			   "AMIC1", "MIC BIAS1",
> +			   "AMIC2", "MIC BIAS2",
> +			   "VA DMIC0", "MIC BIAS3",
> +			   "VA DMIC1", "MIC BIAS3",
> +			   "VA DMIC2", "MIC BIAS1",
> +			   "VA DMIC3", "MIC BIAS1",
> +			   "TX SWR_ADC0", "ADC1_OUTPUT",
> +			   "TX SWR_ADC1", "ADC2_OUTPUT",
> +			   "TX SWR_ADC2", "ADC3_OUTPUT",
> +			   "TX SWR_DMIC0", "DMIC1_OUTPUT",
> +			   "TX SWR_DMIC1", "DMIC2_OUTPUT",
> +			   "TX SWR_DMIC2", "DMIC3_OUTPUT",
> +			   "TX SWR_DMIC3", "DMIC4_OUTPUT",
> +			   "TX SWR_DMIC4", "DMIC5_OUTPUT",
> +			   "TX SWR_DMIC5", "DMIC6_OUTPUT",
> +			   "TX SWR_DMIC6", "DMIC7_OUTPUT",
> +			   "TX SWR_DMIC7", "DMIC8_OUTPUT";
> +
> +		qcom,msm-mbhc-hphl-swh = <1>;
> +		qcom,msm-mbhc-gnd-swh = <1>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		#sound-dai-cells = <0>;
> +
> +		dai-link@0 {
> +			link-name = "MAX98360A";
> +			reg = <0>;
> +
> +			cpu {
> +				sound-dai = <&lpass_cpu MI2S_SECONDARY>;
> +			};
> +
> +			codec {
> +			   sound-dai = <&max98360a>;

I have no clue what happened here. This was correct code before, now it
is not. It turns out it was not just a move of code. If you just
cut+paste, would be fine, but you changed it during moving and now we
have to review it. Reviewing such diffs is difficult if not impossible,
so we have no way to validate, maybe except comparing de-compiled dtbs
(dtx_diff, fdtdump). Did you do it?

Otherwise I do not see a way how can we be sure this code is correct if
you do not cut+paste but change the code in the meantime.

Best regards,
Krzysztof

Re: [PATCH 2/7] arm64: dts: qcom: sc7280: audioreach: Add sound node

[Krzysztof Kozlowski]

On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Add sound node for sc7280 based audioreach platforms.
> 
> Include audioreach dtsi into crd-rev3 platform specific dts file.
> Also remove phandle to sound node, as audio routing is same as
> audioreach specific dtsi file.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts         |  25 +----
>  .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi  | 112 +++++++++++++++++++++
>  2 files changed, 113 insertions(+), 24 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
> index b024626..aea8cbd 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
> @@ -8,7 +8,7 @@
>  /dts-v1/;
>  
>  #include "sc7280-idp.dtsi"
> -#include "sc7280-audio-idp.dtsi"
> +#include "sc7280-herobrine-audioreach-wcd9385.dtsi"
>  #include "sc7280-idp-ec-h1.dtsi"
>  
>  / {
> @@ -88,29 +88,6 @@ ap_ts_pen_1v8: &i2c13 {
>  	pins = "gpio51";
>  };
>  
> -&sound {
> -	audio-routing =
> -		"IN1_HPHL", "HPHL_OUT",
> -		"IN2_HPHR", "HPHR_OUT",
> -		"AMIC1", "MIC BIAS1",
> -		"AMIC2", "MIC BIAS2",
> -		"VA DMIC0", "MIC BIAS1",
> -		"VA DMIC1", "MIC BIAS1",
> -		"VA DMIC2", "MIC BIAS3",
> -		"VA DMIC3", "MIC BIAS3",
> -		"TX SWR_ADC0", "ADC1_OUTPUT",
> -		"TX SWR_ADC1", "ADC2_OUTPUT",
> -		"TX SWR_ADC2", "ADC3_OUTPUT",
> -		"TX SWR_DMIC0", "DMIC1_OUTPUT",
> -		"TX SWR_DMIC1", "DMIC2_OUTPUT",
> -		"TX SWR_DMIC2", "DMIC3_OUTPUT",
> -		"TX SWR_DMIC3", "DMIC4_OUTPUT",
> -		"TX SWR_DMIC4", "DMIC5_OUTPUT",
> -		"TX SWR_DMIC5", "DMIC6_OUTPUT",
> -		"TX SWR_DMIC6", "DMIC7_OUTPUT",
> -		"TX SWR_DMIC7", "DMIC8_OUTPUT";
> -};
> -
>  &wcd9385 {
>  	pinctrl-names = "default", "sleep";
>  	pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> new file mode 100644
> index 0000000..1eac94e1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> @@ -0,0 +1,112 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * sc7280 device tree source for boards using Max98360 and wcd9385 codec
> + * along with ADSP
> + *
> + * Copyright (c) 2022, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/sound/qcom,q6afe.h>
> +#include <dt-bindings/soc/qcom,gpr.h>
> +#include <dt-bindings/clock/qcom,lpass-sc7280.h>
> +
> +/{
> +	/* BOARD-SPECIFIC TOP LEVEL NODES */
> +	sound: sound {
> +		compatible = "google,sc7280-herobrine";
> +		model = "SC7280-AUDIOREACH";
> +		status = "okay";
> +		adsp-mode;
> +		audio-routing =
> +		   "IN1_HPHL", "HPHL_OUT",
> +		   "IN2_HPHR", "HPHR_OUT",
> +		   "AMIC1", "MIC BIAS1",
> +		   "AMIC2", "MIC BIAS2",
> +		   "VA DMIC0", "MIC BIAS1",
> +		   "VA DMIC1", "MIC BIAS1",
> +		   "VA DMIC2", "MIC BIAS3",
> +		   "VA DMIC3", "MIC BIAS3",
> +		   "TX SWR_ADC0", "ADC1_OUTPUT",
> +		   "TX SWR_ADC1", "ADC2_OUTPUT",
> +		   "TX SWR_ADC2", "ADC3_OUTPUT",
> +		   "TX SWR_DMIC0", "DMIC1_OUTPUT",
> +		   "TX SWR_DMIC1", "DMIC2_OUTPUT",
> +		   "TX SWR_DMIC2", "DMIC3_OUTPUT",
> +		   "TX SWR_DMIC3", "DMIC4_OUTPUT",
> +		   "TX SWR_DMIC4", "DMIC5_OUTPUT",
> +		   "TX SWR_DMIC5", "DMIC6_OUTPUT",
> +		   "TX SWR_DMIC6", "DMIC7_OUTPUT",
> +		   "TX SWR_DMIC7", "DMIC8_OUTPUT";
> +
> +		qcom,msm-mbhc-hphl-swh = <1>;
> +		qcom,msm-mbhc-gnd-swh = <1>;
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		#sound-dai-cells = <0>;
> +
> +		dai-link@0 {
> +			link-name = "WCD9385 Playback";
> +			reg = <0>;
> +
> +			cpu {
> +				sound-dai = <&q6apmbedai  RX_CODEC_DMA_RX_0>;

Just one space.

> +			};
> +			codec {
> +				sound-dai = <&wcd9385 0>, <&swr0 0>, <&lpass_rx_macro 0>;
> +			};
> +			platform {
> +				sound-dai = <&q6apm>;
> +			};
> +		};
> +
> +		dai-link@1 {
> +			link-name = "WCD9385 Capture";
> +			reg = <1>;
> +
> +			cpu {
> +				sound-dai = <&q6apmbedai  TX_CODEC_DMA_TX_3>;
> +			};
> +			codec {
> +				sound-dai = <&wcd9385 1>, <&swr1 0>, <&lpass_tx_macro 0>;
> +			};
> +			platform {
> +				sound-dai = <&q6apm>;
> +			};
> +		};
> +
> +		dai-link@2 {
> +			link-name = "MAX98360A";

Amplifier playback?

> +			reg = <3>;
> +
> +			cpu {
> +				sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>;
> +			};
> +
> +			codec {
> +				sound-dai =	 <&max98360a>;

No redundant whitespaces around =.


> +			};
> +
> +			platform {
> +				sound-dai = <&q6apm>;
> +			};
> +		};
> +
> +		dai-link@3 {
> +			link-name = "DMIC";
> +			reg = <4>;
> +
> +			cpu {
> +				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
> +			};
> +
> +			codec {
> +				sound-dai = <&lpass_va_macro 0>;
> +			};
> +
> +			platform {
> +				sound-dai = <&q6apm>;
> +			};
> +		};
> +	};
> +};

Best regards,
Krzysztof

Re: [PATCH 3/7] arm64: dts: qcom: sc7280: audioreach: Add lpass pil node

[Krzysztof Kozlowski]

On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Add lpass pil node for sc7280 based audioreach platforms.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
> This patch depends on:
>     -- https://lore.kernel.org/linux-remoteproc/6e0590af-0bd1-cbef-c573-fa62b5bc9e63@quicinc.com/
> 
>  .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi  | 99 ++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> index 1eac94e1..0ce8755 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> @@ -110,3 +110,102 @@
>  		};
>  	};
>  };
> +
> +&soc {
> +	qcom,lpass@3000000 {

Not correct name.

Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

Additionally, why this is not part of SoC DTSI? Defining SoC nodes in
other DTSI files is not readable and not maintainable.

> +		compatible = "qcom,sc7280-adsp-pil";
> +		reg = <0 0x03000000 0 0x5000>,
> +			<0 0x0355b000 0 0x10>;

Misaligned.

> +
> +		reg-names = "qdsp6ss_base",
> +			"lpass_efuse";

Misaligned.

> +
> +		interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
> +					<&adsp_smp2p_in 0 0>,
> +					<&adsp_smp2p_in 1 0>,
> +					<&adsp_smp2p_in 2 0>,
> +					<&adsp_smp2p_in 3 0>,
> +					<&adsp_smp2p_in 7 0>;

Misaligned.

What are the trailing '0'?

> +
> +		interrupt-names = "wdog", "fatal", "ready",
> +			"handover", "stop-ack",  "shutdown-ack";
> +		qcom,qmp = <&aoss_qmp>;
> +
> +		clocks = <&rpmhcc RPMH_CXO_CLK>,
> +			<&gcc GCC_CFG_NOC_LPASS_CLK>,
> +			<&lpasscc LPASS_QDSP6SS_XO_CLK>,
> +			<&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
> +			<&lpasscc LPASS_QDSP6SS_CORE_CLK>;
> +
> +		clock-names = "xo", "gcc_cfg_noc_lpass",
> +				"lpass_qdsp6ss_xo",
> +				"lpass_qdsp6ss_sleep",
> +				"lpass_qdsp6ss_core";
> +
> +		iommus = <&apps_smmu 0x1800 0x0>;
> +
> +		power-domains =	<&rpmhpd SC7280_LCX>;
> +		power-domain-names = "lcx";
> +		required-opps = <&rpmhpd_opp_nom>;
> +
> +		resets = <&aoss_reset AOSS_CC_LPASS_RESTART>,
> +			<&pdc_reset PDC_AUDIO_SYNC_RESET>;
> +
> +		reset-names = "cc_lpass", "pdc_sync";
> +
> +		qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
> +
> +		memory-region = <&adsp_mem>;
> +
> +		status = "okay";

Why do you need this?
> +
> +		qcom,smem-states = <&adsp_smp2p_out 0>;
> +		qcom,smem-state-names = "stop";
> +
> +		glink-edge {
> +			interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
> +						IPCC_MPROC_SIGNAL_GLINK_QMP
> +						IRQ_TYPE_EDGE_RISING>;
> +			mboxes = <&ipcc IPCC_CLIENT_LPASS
> +					IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> +			label = "lpass";
> +			qcom,remote-pid = <2>;
> +
> +			gpr {
> +				compatible = "qcom,gpr";
> +				qcom,glink-channels = "adsp_apps";
> +				qcom,domain = <GPR_DOMAIN_ID_ADSP>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				qcom,intents = <512 20>;
> +
> +				q6apm: q6apm {

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

It's not even passing regular test - build with W=1...

> +					reg = <GPR_APM_MODULE_IID>;

Where did you include file that define?

> +					compatible = "qcom,q6apm";
> +					#sound-dai-cells = <0>;
> +					q6apmdai: dais {
> +						compatible = "qcom,q6apm-dais";
> +						#sound-dai-cells = <1>;
> +						iommus = <&apps_smmu 0x1801 0x0>;
> +					};
> +

Best regards,
Krzysztof

Re: [PATCH 4/7] arm64: dts: qcom: sc7280: audioreach: Update lpasscc reg property

[Krzysztof Kozlowski]

On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Update lpasscc register mapping for avoiding memory regions conflict with
> ADSP pil node.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> index 0ce8755..a750f05 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> @@ -111,6 +111,14 @@
>  	};
>  };
>  
> +&lpasscc {
> +	reg = <0 0x03c04000 0 0x4>,
> +		<0 0x032a9000 0 0x1000>;

Misaligned.

> +	reg-names = "top_cc", "reset-cgcr";

I have doubts this was tested... git grep shows 0 answers.

> +	#reset-cells = <1>;

Why all these are not part of SoC DTSI?

> +	status = "okay";

Why?

> +};
> +
>  &soc {
>  	qcom,lpass@3000000 {
>  		compatible = "qcom,sc7280-adsp-pil";

Best regards,
Krzysztof

Re: [PATCH 5/7] arm64: dts: qcom: sc7280: audioreach: Add CGCR reset property

[Krzysztof Kozlowski]

On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Add CGCR register reset property for both RX and TX soundwire
> slave devices.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
> This patch depends on:
>     -- https://lore.kernel.org/linux-clk/1671618061-6329-1-git-send-email-quic_srivasam@quicinc.com/
> 
>  .../arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> index a750f05..ce5d69e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> @@ -217,3 +217,12 @@
>  		};
>  	};
>  };
> +
> +&swr0 {
> +	resets = <&lpasscc LPASS_AUDIO_SWR_RX_CGCR>;
> +};
> +
> +&swr1 {

Why here not in SoC DTSI?

> +	resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
> +};
> +

Are you adding stray new lines?

Best regards,
Krzysztof

Re: [PATCH 6/7] arm64: dts: qcom: sc7280: audioreach: Update VA/RX/TX macro clock nodes

[Krzysztof Kozlowski]

On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Update VA, RX and TX macro and lpass_tlmm clock properties and
> enable them.

No. You need to describe why you are doing. Not just "Update".
Everything is an "update".

> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
>  .../qcom/sc7280-herobrine-audioreach-wcd9385.dtsi  | 43 ++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> index ce5d69e..a0061ef 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> @@ -119,6 +119,49 @@
>  	status = "okay";
>  };
>  
> +&lpass_tlmm {
> +	clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +		 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> +
> +	clock-names = "core", "audio";
> +	reg = <0 0x033c0000 0x0 0x20000>,
> +	      <0 0x03550000 0x0 0xa100>;

1. Why are you doing it?
2. Why here, not in DTSI?
3. Does it pass dtbs_check?

> +};
> +
> +&lpass_va_macro {
> +	clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +		 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
> +		 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
> +
> +	clock-names = "mclk", "macro", "dcodec";
> +	power-domain-names = "null";

???

This code looks like not taken from mainline, but some odd tree. Please
work on mainline. Do you see anywhere names called "null"?

Best regards,
Krzysztof

Re: [PATCH 7/7] arm64: dts: qcom: sc7280: audioreach: Disable legacy path clock nodes

[Krzysztof Kozlowski]

On 22/12/2022 10:42, Srinivasa Rao Mandadapu wrote:
> Disable legacy path clock nodes to avoid conflicts with audioreach
> clock node.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
>  .../boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi   | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> index a0061ef..dce0114 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audioreach-wcd9385.dtsi
> @@ -162,6 +162,18 @@
>  	status = "okay";
>  };
>  
> +&lpass_core {
> +	status = "disabled";
> +};
> +
> +&lpass_aon {
> +	status = "disabled";
> +};
> +
> +&lpass_audiocc {
> +	status = "disabled";
> +};

Keep nodes sorted.


Best regards,
Krzysztof