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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29651c7409esm177939655ad.64.2025.11.11.03.44.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Nov 2025 03:44:45 -0800 (PST) Message-ID: <507b121b-98c0-4632-8a61-e9d7a6a13a3e@oss.qualcomm.com> Date: Tue, 11 Nov 2025 19:44:36 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] clk: qcom: rpmh: Add support for Kaanapali rpmh clocks To: Dmitry Baryshkov , Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , jingyi.wang@oss.qualcomm.com, Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251030-gcc_kaanapali-v2-v2-0-a774a587af6f@oss.qualcomm.com> <20251030-gcc_kaanapali-v2-v2-4-a774a587af6f@oss.qualcomm.com> Content-Language: en-US From: "Aiqun(Maria) Yu" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: cUy2LLnSCZPEAyWGJxTREOVO_07l9KrE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTExMDA5MiBTYWx0ZWRfX/BXeRs4GC+3h L+Ty+nqiKtKFDZgtzbyqBjX3V5g6Flx0ZpoZZ6BIRV609RLX9+h9jxzguXJU13eNWcQ0Xpajipq O9PIWLvO8mg5RWwaphS7tixvidc9xiaJlWI5p6JQTywkdB2453PQUXhtpq8FFj+i3Re5tnOv48z dta5z3YtUcuLt6bPUashgPKqXbxBGl1nTpWo4VNrtwpnGxNblrhMdLYhDsVFin/UzMviyLzTARm noVmdi30rWWoEcUd2DJlYFnZPeLCkOz0N5l9Fxu0NiXZw1JvqpewpLss4FF6leS5ySxwpMRjDQG lSCMyjpCmur79nvhF7pccSBbO3oupx/TG0IWZSh3pwKqT1XCsF8CBj41ISG5JIryjiSPqOaWj3L BN/SUzjy6e9uKh8E6V18E3epVGuyVA== X-Proofpoint-ORIG-GUID: cUy2LLnSCZPEAyWGJxTREOVO_07l9KrE X-Authority-Analysis: v=2.4 cv=d4b4CBjE c=1 sm=1 tr=0 ts=691321ae cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=lvgvr5Ydm3pkVxXdM2UA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-11_02,2025-11-11_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 adultscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511110092 On 11/11/2025 6:46 PM, Dmitry Baryshkov wrote: > On Thu, Oct 30, 2025 at 04:39:07PM +0530, Taniya Das wrote: >> Add the RPMH clocks present in Kaanapali SoC. >> >> Signed-off-by: Jingyi Wang >> Signed-off-by: Taniya Das >> --- >> drivers/clk/qcom/clk-rpmh.c | 42 ++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 42 insertions(+) >> >> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c >> index 1a98b3a0c528c24b600326e6b951b2edb6dcadd7..fd0fe312a7f2830a27e6effc0c0bd905d9d5ebed 100644 >> --- a/drivers/clk/qcom/clk-rpmh.c >> +++ b/drivers/clk/qcom/clk-rpmh.c >> @@ -395,6 +395,19 @@ DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1); >> DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1); >> DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1); >> >> +DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2_e0, "C6A_E0", 2); >> +DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2_e0, "C7A_E0", 2); >> +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2_e0, "C8A_E0", 2); Shall this suffix necessary to have e0? >> + >> +DEFINE_CLK_RPMH_VRM(rf_clk1, _a_e0, "C1A_E0", 1); >> +DEFINE_CLK_RPMH_VRM(rf_clk2, _a_e0, "C2A_E0", 1); > > What is the difference between these clocks and clk[3458] defined few > lines above? Why are they named differently? If the other name is > incorrect, please fix it. Good shot. Only now I can understand the previous comments. IMO for kaanapali Taniya was addressed to have the right rf_clkN naming here. I think the point is glymur is not using "rf_clkN" for rf_clk, sm8750 is not using "ln_bb_clkN" instead it is using clkN: static struct clk_hw *sm8750_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a2.hw, [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a2_ao.hw, [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, }; static struct clk_hw *glymur_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, [RPMH_RF_CLK3] = &clk_rpmh_clk3_a.hw, [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a_ao.hw, [RPMH_RF_CLK4] = &clk_rpmh_clk4_a.hw, [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a_ao.hw, [RPMH_RF_CLK5] = &clk_rpmh_clk5_a.hw, [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a_ao.hw, }; > >> + >> +DEFINE_CLK_RPMH_VRM(rf_clk3, _a2_e0, "C3A_E0", 2); >> +DEFINE_CLK_RPMH_VRM(rf_clk4, _a2_e0, "C4A_E0", 2); >> +DEFINE_CLK_RPMH_VRM(rf_clk5, _a2_e0, "C5A_E0", 2); >> + >> +DEFINE_CLK_RPMH_VRM(div_clk1, _a4_e0, "C11A_E0", 4); >> + >> DEFINE_CLK_RPMH_BCM(ce, "CE0"); >> DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); >> DEFINE_CLK_RPMH_BCM(ipa, "IP0"); >> @@ -901,6 +914,34 @@ static const struct clk_rpmh_desc clk_rpmh_glymur = { >> .num_clks = ARRAY_SIZE(glymur_rpmh_clocks), >> }; >> >> +static struct clk_hw *kaanapali_rpmh_clocks[] = { >> + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, >> + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, >> + [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_a4_e0.hw, >> + [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2_e0.hw, >> + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_e0_ao.hw, >> + [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2_e0.hw, >> + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_e0_ao.hw, >> + [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2_e0.hw, >> + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_e0_ao.hw, >> + [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a_e0.hw, >> + [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_e0_ao.hw, >> + [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a_e0.hw, >> + [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_e0_ao.hw, >> + [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a2_e0.hw, >> + [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a2_e0_ao.hw, >> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a2_e0.hw, >> + [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a2_e0_ao.hw, >> + [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a2_e0.hw, >> + [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a2_e0_ao.hw, >> + [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, >> +}; >> + >> +static const struct clk_rpmh_desc clk_rpmh_kaanapali = { >> + .clks = kaanapali_rpmh_clocks, >> + .num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks), >> +}; >> + >> static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, >> void *data) >> { >> @@ -991,6 +1032,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) >> >> static const struct of_device_id clk_rpmh_match_table[] = { >> { .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur}, >> + { .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali}, >> { .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos}, >> { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, >> { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, >> >> -- >> 2.34.1 >> > -- Thx and BRs, Aiqun(Maria) Yu